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STM32W108HB Datasheet(PDF) 176 Page - STMicroelectronics

Part # STM32W108HB
Description  High-performance, IEEE 802.15.4 wireless system-on-chip with up to 256 Kbytes of embedded Flash memory
PDF  278 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32W108HB Datasheet(HTML) 176 Page - STMicroelectronics

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General-purpose timers
STM32W108HB STM32W108CC STM32W108CB STM32W108CZ
176/278
Doc ID 16252 Rev 14
Hints on using center-aligned mode:
●
When starting in center-aligned mode, the current up-down configuration is used. This
means that the counter counts up or down depending on the value written in the DIR bit
in the TIMx_CR1 register. The DIR and CMS bits must not be changed at the same
time by the software.
●
Writing to the counter while running in center-aligned mode is not recommended as it
can lead to unexpected results. In particular:
●
The direction is not updated the value written to the counter that is greater than the
auto-reload value (TIMx_CNT > TIMx_ARR). For example, if the counter was counting
up, it continues to count up.
●
The direction is updated if when 0 or the TIMx_ARR value is written to the counter, but
no update event is generated.
●
The safest way to use center-aligned mode is to generate an update by software
(setting the UG bit in the TIMx_EGR register) just before starting the counter, and not to
write the counter while it is running.
10.1.10
One-pulse mode
One-pulse mode (OPM) is a special case of the previous modes. It allows the counter to be
started in response to a stimulus and to generate a pulse with a programmable length after
a programmable delay.
Starting the counter can be controlled through the slave mode controller. Generating the
waveform can be done in output compare mode or PWM mode. Select OPM by setting the
OPM bit in the TIMx_CR1 register. This makes the counter stop automatically at the next
update event.
A pulse can be correctly generated only if the compare value is different from the counter
initial value. Before starting (when the timer is waiting for the trigger), the configuration must
be:
●
In up-counting: TIMx_CNT < TIMx_CCRy
≤TIMx_ARR (in particular, 0 < TIMx_CCRy),
●
In down-counting: TIMx_CNT > TIMx_CCRy.



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