© 2002 QuickLogic Corporation
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QL82SD Device Data Sheet Rev C
Preliminary
43
www.quicklogic.com
When I/O pins are unused, the OE controls can be permanently disabled, allowing the output
cell register to be used for registered feedback into the logic array.
I/O cell registers are controlled by clock, clock enable, and reset signals, which can come
from the regular routing resources, from one of the global networks, or from two input pins
per bank of I/O's. The CLK and RESET signals share a common line, while the clock enables
for each register can be independently controlled. Additionally, the output and enable
registers will increase a device's register count. The addition of an output register will also
decrease the TCO. Since the output register does not need to drive the routing, the length
of the output path is also reduced.
Extra registers add more inputs and outputs to the I/O structure. Extra routing resources are
added to connect the I/O structure to the other parts of the device.
I/O interface support is programmable on a per bank basis. There are 4 I/O banks per chip.
Users can not mix a 2.5 volt I/O with 3.3 volt I/O on the same I/O bank. Figure 52 illustrates
the multiple I/O bank configurations.
Figure 52: Multiple I/O Bank Configurations
Each I/O bank is independent of other I/O banks and each I/O bank has its own VCCIO and
VREF supplies. A mixture of different I/O standards can be used on the device; however, there
is a limitation as to which I/O standards can be supported within a given bank. Differential
I/O can be shared with non differential I/O. There can only be one VREF and one VCCIO per
bank.
Programmable Slew Rate
Each I/O has programmable slew rate capability. The rate is programmable to one of two
slew rates: either fast or slow. The slower rate can be used to reduce ground bounce noise.
The slow slew rate is 1 V/ns under typical conditions. The fast slew rate is 2.8 V/ns
Table 34: 3.3 V Slew Rate
VCCIO = 3.3 V
Fast Slew
Slow Slew
Rising Edge
2.8 V/nS
1.0 V/vS
Falling Edge
2.86 V/nS
1.0 V/nS
VCCIO 0
VREF 0
I/O Bank 0
VCCIO 1
VREF 1
I/O Bank 2
VCCIO 2
VREF 2
VCCIO 3
VREF 3
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