TLE7232G datasheet(25/36 Pages) INFINEON

25 / 36 page

SPI Driver for Enhanced Relay Control

SPIDER - TLE 7232G

Serial Peripheral Interface (SPI)

Data Sheet

V1.0, 2005-09-30

4.4

Serial Peripheral Interface (SPI)

The diagnosis and control interface is based on a serial peripheral interface (SPI).

The SPI is a full duplex synchronous serial slave interface, which uses four lines: SO, SI,

SCLK and CS. Data is transferred by the lines SI and SO at the data rate given by SCLK.

The falling edge of CS indicates the beginning of a data access. Data is sampled in on

line SI at the falling edge of SCLK and shifted out on line SO at the rising edge of SCLK.

Each access must be terminated by a rising edge of CS. A modulo 8 counter ensures

that data is taken only, when a multiple of 8 bit has been transferred. The interface

provides daisy chain capability.

Figure 10

Serial Peripheral Interface

The SPI protocol is described in Section 4.4.5. It is reset to the default values after

power-on reset or a low signal at pin RST.

4.4.1

SPI Signal Description

CS - Chip Select: The system micro controller selects the SPIDER - TLE 7232G by

means of the CS pin. Whenever the pin is in low state, data transfer can take place.

When CS is in high state, any signals at the SCLK and SI pins are ignored and SO is

forced into a high impedance state.

CS High to Low transition:

• The diagnosis information is transferred into the shift register.

CS Low to High transition:

• Command decoding is only done, when after the falling edge of CS exactly a multiple

(1, 2, 3, …) of eight SCLK signals have been detected.

• Data from shift register is transferred into the input matrix register.

• The diagnosis flags are cleared.

SCLK - Serial Clock: This input pin clocks the internal shift register. The serial input (SI)

transfers data into the shift register on the falling edge of SCLK while the serial output

MSB

SPI.emf

LSB

SCLK

time

TLE7232G Datasheet(PDF) 25 Page - Infineon Technologies AG