M5M29KB datasheet(6/32 Pages) RENESAS

6 / 32 page

M5M29KB/T331AVP

Renesas LSIs

Rev.1.0_48a_bezz

33,554,432-BIT (4,194,304-WORD BY 8-BIT /2,097,152-WORD BY 16-BIT)

CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY

We can normally read device identifier codes when Read

Device Identifier Code Command (90H) is written to the

command

latch.

Following

the

command

write,

the

manufacturer code and the device code can be read from

A0 address 0H and 1H in a bank address, respectively.

The device is in Read Array mode on initial device power

up and after exit from deep power down, or by writing FFH

to the Command User Interface. After starting the internal

operation the device is set to the read status register mode

automatically.

Automated block erase is initiated by writing the Block

Erase command of 20H followed by the Confirm

command of D0H.

An address within the block to be

erased is required.

The WSM executes iterative erase

pulse application and erase verify operation.

Word / Byte program is executed by a two-command

sequence. The Word/Byte program Setup command of

40H is written to the Command Interface, followed by a

second write specifying the address and data to be written.

The WSM controls the program pulse application and

verify operation.

Page Program allows fast programming of 128 words/

256 bytes of data. Writing of 41H initiates the page

program operation for the Data area. From 2nd cycle to

129th cycle(Word mode)/ 257th cycle(Byte mode), write

data must be serially inputted. Address

A6-A0(Word

mode)/ A6-A-1(Byte mode) have to be incremented from

00H to 7FH. After completion of data loading, the WSM

controls

the

program

pulse

application

and

verify

operation.

Single data load to the page buffer is performed by

writing 74H followed by a second write specifying the

column address and data. Distinct data up to 128word

can be loaded to the page buffer by this two-command

sequence. On the other hand, all of the loaded data to the

page buffer is programmed simultaneously by writing

Page Buffer to Flash command of 0EH followed by the

confirm

command

D0H.

After

completion

programming the data on the page buffer is cleared

automatically.

The device operations are selected by writing specific

software command into the Command User Interface.

Software Command Definitions

The Status Register is read after writing the Read Status

Also, after starting the internal operation the device is set to

the Read Status Register mode automatically.

The contents of Status Register are latched on the later

falling edge of OE# or CE#. When status read is required,

OE# or CE# must be toggled every status read.

The Erase Status, Program Status and Block Status bits

are set to "1"s by the Write State Machine and can only

be reset by the Clear Status Register command of 50H.

These bits indicate various failure conditions.

A) Word / Byte Program (40H)

Program Commands

Block Erase / Confirm Command (20H/D0H)

Clear Status Register Command (50H)

Read Array Command (FFH)

Read Status Register Command (70H)

Read Device Identifier Command (90H)

Page Read Command (F3H)

B) Page Program for Data Blocks (41H)

C) Single Data Load to Page Buffer (74H)

/ Page Buffer to Flash (0EH/D0H)

The Page Read command (F3H) timing can be used by

writing the first command and CE# falls VIL or changing the

address(A20-A2) is necessary to start activating page read

mode. This command is fast random 4 words read. During

the read cycle operation it is necessary to fix CE# low and

change addresses which are defined by A0 and A1(or A-1

to A1) at random continuously.

The mode is kept until RP# is set to VIL or this chip is

powered down.

The first read of Page Read timing is the same as normal

read (ta(CE)). CE# should be fallen VIL. The read timing

after the first is fast read (ta(PAD)).

In the page read mode the upper address(A20-A2) is

supposed not to be clocked during read operation.

Otherwise the access time is as same as normal read.

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