M5M29KB/T331AVP

Renesas LSIs

Rev.1.0_48a_bezz

19

33,554,432-BIT (4,194,304-WORD BY 8-BIT /2,097,152-WORD BY 16-BIT)

CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY

AC waveforms for Page Read Operation

Byte AC Waveforms for Read Operation

ADDRESS

A20-A0

CE#

OE#

BYTE#

DATA

D7-D0

Address Valid

High-Z

V

IH

V

IL

V

IH

V

IL

V

IH

V

IL

V

IH

V

IL

Output Valid

V

OH

V

OL

DATA

D14-D8

V

OH

V

OL

High-Z

Valid

Valid

Valid

D15/A-1

Address Valid

V

IH

V

IL

D15

A-1

Address Valid

When BYTE# = VIH, CE# = OE# = VIL, D15/A-1 is output status. At this time, input signal must not be applied.

1st Address

CE#

WE#

High-Z

DATA

F3H

Page Address Valid

Address

Address Valid (Voluntary Address)

OE#

Valid

2nd

~

Nth

Valid

Valid

Valid

- After inputting Page Read Command F3H, it is necessary to make CE# “H” pulse more than 30ns (tCEPH).

And after inputting Page Read Command F3H, it is also necessary to keep 30ns to recover before starting read

after WE# rises “H” in case of changing address(es) and CE#=“L”.

- Once Page Read mode is valid, the mode is kept until RP# is set to VIL or the chip is powered off.

- Word mode(BYTE#=VIH):N=4, Byte mode(BYTE#=VIL):N=8