M5M29KB/T331AVP

Renesas LSIs

Rev.1.0_48a_bezz

12

33,554,432-BIT (4,194,304-WORD BY 8-BIT /2,097,152-WORD BY 16-BIT)

CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY

Data

1)

Data

1)

Data

1)

(DQ0-15/DQ0-7)

(DQ0-15/DQ0-7)

(DQ0-15/DQ0-7)

Word/Byte Program

Write

Bank

60H

Write

Bank

Block

6)

Write

Bank

ACH

Page Program

Write

Bank

60H

Write

Bank

Block

6)

Write

Bank

ACH

Page Buffer to Flash

Write

Bank

60H

Write

Bank

Block

6)

Write

Bank

ACH

Block Erase/Confirm

Write

Bank

60H

Write

Bank

Block

6)

Write

Bank

ACH

Clear Page Buffer

Write

Bank

60H

Write

Bank

Block

6)

Write

Bank

ACH

Single Data Load to Page Buffer

Write

Bank

60H

Write

Bank

Block

6)

Write

Bank

ACH

Flash to Page Buffer

Write

Bank

60H

Write

Bank

Block

6)

Write

Bank

ACH

Data

1)

Data

1)

(DQ0-15/DQ0-7)

(DQ0-15/DQ0-7)

Word/Byte Program

Write

Bank

Block#

6)

Write

Bank

7BH

Page Program

Write

Bank

Block#

6)

Write

Bank

7BH

Page Buffer to Flash

Write

Bank

Block#

6)

Write

Bank

7BH

Block Erase/Confirm

Write

Bank

Block#

6)

Write

Bank

7BH

Clear Page Buffer

Write

Bank

Block#

6)

Write

Bank

7BH

Single Data Load to Page Buffer

Write

Bank

Block#

6)

Write

Bank

7BH

Flash to Page Buffer

Write

Bank

Block#

6)

Write

Bank

7BH

Data

1)

Data

Data

(DQ0-15/DQ0-7)

(DQ0-15/DQ0-7)

(DQ0-15/DQ0-7)

Word/Byte Program

Write

Bank

40H

Write

WA

2)

WD

2)

Page Program

Write

Bank

41H

Write

WA0

3)

WD0

3)

Write

WAn

3)

WDn

3)

Page Buffer to Flash

Write

Bank

0EH

Write

WA

4)

D0H

1)

Block Erase/Confirm

Write

Bank

20H

Write

BA

5)

D0H

1)

Clear Page Buffer

Write

X

55H

Write

X

D0H

1)

Single Data Load to Page Buffer

Write

Bank

74H

Write

WA

2)

WD

2)

Flash to Page Buffer

Write

Bank

F1H

Write

RA

7)

D0H

1)

8th-134th Bus Cycles(Word mode)

8th-262th Bus Cycles(Byte mode)

Mode

Address

Setup Command for

Software Lock Release

Setup Command for

Program or Erase Operations

6th Bus Cycle

7th Bus Cycle

Setup Command for

Software Lock Release

4th Bus Cycle

5th Bus Cycle

Mode

Address

3rd Bus Cycle

Mode

Address

1st Bus Cycle

2nd Bus Cycle

7) RA=Read Address: A20-A7 (block address, page address) must be valid.

Command List (WP# =VIL)

Software Command Definition

Software lock release operation needs following consecutive 7bus cycles.Moreover, additional 127(255) bus cycles are

needed for page program operation.

Address

DQ7

DQ6

DQ5

DQ4

DQ3

DQ2

DQ1

DQ0

Block

fixed 0

fixed 0

A20

A19

A18

A17

A16

A15

Block#

fixed 0

fixed 0

A20#

A19#

A18#

A17#

A16#

A15#

1) In the case of word mode(BYTE#=VIH) upper byte data (DQ15-DQ8) is ignored.

2) WA=Write Address, WD=Write Data

3) WA0, WAn=Write Address, WD0, WDn=Write Data. Write address and write data must be provided sequentially

from 00H to 7FH for A6-A0(word mode) and from 00H to FFH for A6-A-1(byte mode), respectively.

Page size is 128 words (128-word x 16-bit/ word mode) or Page size is 256 bytes (256-word x 8-bit/ byte mode),

and also A20-A7 (block address, page address) must be valid.

4) WA=Write Address: A20-A7 (block address, page address) must be valid.

5) BA=Block Address : A20-A12[Bank(I)], A20-A15 [Bank(II), Bank(III), Bank(IV)]

6) Block=Block Address: A20-A15, Block#=A20#-A15# must be valid.