| Electronic Components Datasheet Search |
|
M95P16-IXCS/EF Datasheet(PDF) 10 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
M95P16-IXCS/EF Datasheet(HTML) 10 Page - STMicroelectronics |
|
10 / 63 page ![]() 3.6 Write protect (W-DQ2) This pin is a CMOS input with no internal pull-up/down, and an output push-pull buffer. The main purpose of this signal is to freeze the size of the area of memory protected against Write instructions (as specified by the values in the BPn and TB bits of the Status register). This pin must be driven either high or low, and must be stable during all Write instructions. It supports dual and quad output read (see Section 4.3 and Section 4.4). With the fast read quad output command, the Write protect pin (W-DQ2) becomes an output pin, after the last bit of the third address bytes of the command. In conjunction with other pins, this allows four bits of data on DQ2 to be clocked-in on every falling edge of SCK. For consistency with the SPI nomenclature, this pin is referred to as W, unless specifically addressing the Quad output mode, in which case it is referred to as DQ2. 3.7 VCC (VCC, supply voltage) VCC is the device core power supply. 3.8 VSS (VSS, ground) VSS is the reference for all signals, including the VCC supply voltage. M95P16-I M95P16-E Write protect (W-DQ2) DS13710 - Rev 1 page 10/63 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |