M95P16-IXCSSLASHEF datasheet(22/63 Pages) STMICROELECTRONICS

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6.1

Write enable (06h)

The write enable (WREN) instruction sets the write enable latch (WEL) bit in the status register to 1. The WEL

bit must be set before every page program, page write, page erase, sector erase, block erase, chip erase, write

status register, write volatile register, and write identification page instruction.

The write enable instruction is entered by driving S low, shifting the instruction code 06h into the data input (D)

pin on the rising edge of C, and then driving S high. The S pin must be driven high after the eighth bit has been

latched. If this is not done the write enable instruction is not executed.

Figure 7. Write enable

MS54391V1

WREN instruction

High impedance

6.2

Write disable (04h)

The write disable (WRDI) instruction resets the write enable latch (WEL) bit in the status register to 0. The write

disable instruction is entered by driving S low, shifting the instruction code 04h into the D pin, and then driving S

high.

The S pin must be driven high after the eighth bit has been latched. If this is not done the write disable instruction

is not executed.

Figure 8. Write disable

Write disable instruction

-3

-2

-1

High impedance

MS54396V1

M95P16-I M95P16-E

Write enable (06h)

DS13710 - Rev 1

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M95P16-IXCS/EF Datasheet(PDF) 22 Page - STMicroelectronics