M95P16-IXCSSLASHEF datasheet(28/63 Pages) STMICROELECTRONICS

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6.11

Fast read dual output with one dummy byte (3Bh)

The Fast read dual output with one dummy byte (FDREAD) instruction is similar to the Fast read single output

with one dummy byte (0Bh) instruction, except that data is output on pins DQ1 and DQ0. This allows the data to

be transferred at the highest possible frequency of fC (see Table 27. AC characteristics - Other parameters).

The instruction is initiated by driving the S pin low, then shifting the instruction code 3Bh followed by a 24-bit

address (A23-A0) into the D pin, and finally adding eight dummy clock cycles, as shown in Figure 18. The code

and address bits are latched on the rising edge of the C pin. After the eight dummy clock cycles are received, the

data byte of the addressed memory location is shifted out (MSB first) on the DQ1 and DQ0 pins (every two bits

interleave on the two I/O pins), on the falling edge of C.

The address is automatically incremented to the next higher address after each data byte is shifted out, so the

whole memory can be read out with a Fast read dual instruction. The address counter rolls over to 0 after the

highest address is reached. The instruction is completed by driving the S pin high. During the dummy clock

cycles, the data value on the D pin is Don't care, and the Q pin is high-Z.

Figure 18. Fast read dual output with one dummy byte

A23

A22

A21

High impedance

D-DQ0

Q-DQ1

FDREAD instruction

24-bit address

MS55470V1

Dummy clock cycles

Data Out 2

Data Out 1

M95P16-I M95P16-E

Fast read dual output with one dummy byte (3Bh)

DS13710 - Rev 1

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M95P16-IXCS/EF Datasheet(PDF) 28 Page - STMicroelectronics