M95P16-IXCSSLASHEF datasheet(29/63 Pages) STMICROELECTRONICS

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6.12

Fast read quad output with one dummy byte (6Bh)

The fast read quad output with one dummy byte (FQREAD) instruction is similar to the Fast read dual output with

one dummy byte instruction, except that data is output on four pins (DQ3, DQ2, DQ1 and DQ0). This allows data

to be transferred at the highest possible frequency of fC (see Table 27. AC characteristics - Other parameters).

The instruction is initiated by driving the S pin low, then shifting the instruction code 6Bh, followed by a 24-bit

address (A23-A0) into the D pin, and then adding eight dummy clock cycles as shown in Figure 19. The code and

address bits are latched on the rising edge of the C pin. After the eight dummy clock cycles are received, the data

byte of the addressed memory location is shifted out (MSB first) on the DQ3, DQ2, DQ1 and DQ0 pins (every four

bits interleave on the four I/O pins) on the falling edge of C.

The address is automatically incremented to the next higher address after each data byte is shifted out, so the

whole memory can be read out with a Fast read quad instruction. The address counter rolls over to 0 after the

highest address is reached.

The instruction is completed by driving the S pin high.

During the dummy clock cycles, the data value on the D pin is don't care, and the Q pin is high-Z.

Note:

The W-DQ2 and HOLD-DQ3 pins switch in high-impedance after the last bit of the third address byte of the

instruction.

Figure 19. Fast read quad output with one dummy byte

A23

A22

A21

High impedance

D-DQ0

Q-DQ1

W-DQ2

HOLD-DQ3

FQREAD instruction

24-bit address

High impedance

Dummy clock cycles

Data Out 3

Data Out 2

Data Out 1

D-DQ0

Q-DQ1

W-DQ2

HOLD-DQ3

High impedance

MS69272V1

High impedance

M95P16-I M95P16-E

Fast read quad output with one dummy byte (6Bh)

DS13710 - Rev 1

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