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M95P16-IXCS/EF Datasheet(PDF) 14 Page - STMicroelectronics

Part # M95P16-IXCS/EF
Description  Ultra low power 16 Mbit serial SPI page EEPROM with dual and quad outputs
PDF  63 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

M95P16-IXCS/EF Datasheet(HTML) 14 Page - STMicroelectronics

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Normally, the device is kept selected for the duration of the Hold condition. This ensures that the internal logic
state remains unchanged from the moment of entry into the Hold condition. Deselecting the device during the
Hold condition resets the state of the device. This mechanism can be used to reset the ongoing processes.
Note:
This resets the internal logic, except the WEL and WIP bits of the Status register.
The Hold condition starts when the HOLD signal is driven low when Serial clock (C) is already low (as shown in
Figure 6). If the falling edge does not coincide with C being low, the hold condition starts when C next goes low.
The Hold condition ends on the rising edge of the HOLD signal, if this coincides with C being low. If the rising
edge does not coincide with C being low, the hold condition ends when C next goes low.
Figure 6. Hold condition activation
Hold
condition
Hold
condition
HOLD
C
Figure 6 also shows what happens if the rising and falling edges are not timed to coincide with Serial clock (C)
being low.
To restart communication with the device, it is necessary to drive HOLD high, and then to drive chip select (S) low.
This prevents the device from returning to the hold condition.
4.11
ECC
The error correction code (ECC) is an internal logic function that significantly improves the data integrity of the
device. It is always active, and is transparent for SPI communication.
The ECC offers double-bit correction over 16 bytes (128 bits), and triple-bit error detection. When a 3-error
detection occurs, no correction is applied to the data. The single, double and triple error detection bits are
readable in the Safety register.
The ECC flag information is cumulative, meaning that on the same read instruction the flags are raised
as soon as a correction or a detection occurs, and all flags may be raised. The status bit is detailed in
Section 5.2.2 Safety register.
M95P16-I M95P16-E
ECC
DS13710 - Rev 1
page 14/63



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