M95P16-IXCSSLASHEF datasheet(31/63 Pages) STMICROELECTRONICS

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Figure 21. Block erase

-3

-2

-1

A23

A22

A21

High impedance

BKER instruction

24-bit address

MS55407V1

6.13.3

Sector erase (20h)

The Sector erase (SCER) instruction sets all memory bits within a specified sector (4 Kbytes) to the erased state

of all 1s (FFh). A Write enable instruction must be executed before the device accepts this instruction (Status

code 20h, followed a 24-bit sector address (A23-A0). The instruction is completed by driving S high. The Sector

erase instruction sequence is shown in Figure 22.

Figure 22. Sector erase

A23

A22

A21

High impedance

SCER instruction

24-bit address

MS55408V1

The S pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the Sector

erase instruction is not executed. After S is driven high, the self-timed Sector erase instruction starts, for a time

duration of tSE (see Table 26. Programming times). While the Sector erase cycle is in progress, the Read status

erase cycle. It transits to 0 when the cycle is finished and the device is ready to accept further instructions. After

the Sector erase cycle is complete, the Write enable Latch (WEL) bit in the Status register is cleared to 0. The

Sector erase instruction is not executed if any addressed pages of the sector are protected by the block protection

(BP2, BP1, and BP0) and TB bits. The status is reported with PAMAF and ERF flags (see Table 9. Safety register

format).

M95P16-I M95P16-E

Erase operations

DS13710 - Rev 1

page 31/63

M95P16-IXCS/EF Datasheet(PDF) 31 Page - STMicroelectronics