M95P16-IXCSSLASHEF datasheet(12/63 Pages) STMICROELECTRONICS

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4.2

SPI modes

This device can be driven by a microcontroller through its SPI peripheral running in one of the following modes:

•

CPOL = 0, CPHA = 0

•

CPOL = 1, CPHA = 1

In these modes, input data is latched on the rising edge of the Serial clock (C), and data is output on the falling

edge of the Serial clock (C).

The difference between the modes, as shown in Figure 5, is the polarity of the clock state when the bus master is

in Standby mode and not transferring data:

•

C remains at 0 for (CPOL = 0, CPHA = 0)

•

C remains at 1 for (CPOL = 1, CPHA = 1)

Figure 5. SPI modes supported

MSB

CPOL

CPHA

Because at a given instant only one device is selected, only one device drives the serial data output (n-DQn) at

that time. The other devices are in high-Z. An example of three devices connected to an MCU through an SPI bus

is shown in Figure 4.

4.3

Dual output read

The devices feature a Dual output read mode that allows two bits of data to be clocked out of the device every

clock cycle to improve throughput. With the Fast read dual output command, the D pin becomes an output

(D-DQ0), along with the Q-DQ1 pin.

4.4

Quad output read

The devices feature a Quad output read mode that allows four bits of data to be clocked out of the device on

every clock cycle to improve throughput. With the Fast read quad output command, the D, W and HOLD pins

become outputs (respectively, D-DQ0, W-DQ2, HOLD-DQ3), along with the Q-DQ1 pin.

4.5

Supply voltage

Prior to selecting the memory and issuing instructions to it, a valid and stable supply voltage within the specified

VCC(min) to VCC(max) range must be applied (see Table 18. Operating conditions). This voltage must remain stable

and valid until the end of the transmission of the instruction and, for a modify instruction, until the completion of

the internal write cycle (see Table 26. Programming times).

To ensure a stable DC supply voltage, it is recommended to decouple the VCC line with a suitable capacitor

(between 10 and 100 nF) close to the VCC/VSS device pins.

4.6

Power-up conditions

When the power supply is turned on, VCC rises continuously, from VSS to VCC. During this time, the Chip select

(S) line is not allowed to float, but follows the VCC voltage. It is therefore recommended to connect the S line to

VCC via a suitable pull-up resistor (see Figure 4. Bus master and memory devices on the SPI bus).

M95P16-I M95P16-E

SPI modes

DS13710 - Rev 1

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