TMPR4925 datasheet(189/590 Pages) TOSHIBA

189 / 590 page

Chapter 8 DMA Controller

8-19

8.3.13

Transfer Stall Detection Function

If the period from when a certain channel last performs internal bus access to when the next internal

bus access is performed exceeds the Transfer Stall Detection Interval field (STLTIME) of the DMA

Channel Control Register (DMCCRn), the Transfer Stall Detection bit (STLXFER) of the DMA

Channel Status Register (DMCSRn) is set. An error interrupt is signalled if the Error Interrupt Enable

bit (DMCCRn.INTENE) is set.

In contrast to other error interrupts, DMA transfer is not stopped. Normal DMA transfer is executed

if bus ownership can be obtained. Furthermore, clearing the Transfer Stall Detection

(STLXFER)

resumes transfer stall detection as well.

Setting the Transfer Stall Detection Interval field (STLTIME) to “000” disables the Transfer Stall

Detection function.

8.3.14

Arbitration Among DMA Channels

The DMA Controller has an on-chip DMA Channel Arbiter that arbitrates bus ownership among four

DMA channels that use the internal bus (G-Bus). There are two methods for determining priority: the

round robin method and the fixed priority method. (See Figure 8.3.7.) The Round Robin Priority bit

(RRPT) of the DMA Master Control Register (DMMCR) selects the priority method.

•

Fixed priority (DMMCR.RRPT

= 0)

As shown below, Channel 0 has the highest priority and Channel 3 has the lowest priority.

CH0 > CH1 > CH2 > CH3

•

Round Robin method (DMMCR.RRPT

= 1)

The last channel to perform DMA transfer has the lowest priority.

•

After CH0 DMA transfer execution: CH1 > CH2 > CH3 > CH0

•

After CH1 DMA transfer execution: CH2 > CH3 > CH0 > CH1

•

After CH2 DMA transfer execution: CH3 > CH0 > CH1 > CH2

•

After CH3 DMA transfer execution: CH0 > CH1 > CH2 > CH3

a) Fixed Priority is selected

b) Round Robin Priority is selected

Figure 8.3.7 DMA Channel Arbitration

Channel 0

Channel 1

Channel 2

Channel 3

Channel 0

Channel 2

Channel 1

Channel 3

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