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TMPR4925 Datasheet(PDF) 203 Page - Toshiba Semiconductor |
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TMPR4925 Datasheet(HTML) 203 Page - Toshiba Semiconductor |
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203 / 590 page ![]() Chapter 8 DMA Controller 8-33 8.4.7 DMA Source Address Increment Register (DMSAIRn) 0xB010 (ch. 0) 0xB030 (ch. 1) 0xB050 (ch. 2) 0xB070 (ch. 3) 31 24 23 16 Reserved SADINC[23:16] R/W : Type - : Initial value 15 0 SADINC[15:0] R/W : Type - : Initial value Bits Mnemonic Field Name Description 31:24 Reserved 23:0 SADINC Source Address Increment Source Address Increment (Initial value: undefined, R/W) This field sets the increase/decrease value of the DMA Source Address Register (DMSARn). This value is a 24-bit two’s complement and indicates a byte count. Refer to “8.3.7.1 Channel Register Settings During Single Address Transfer” and “8.3.8.1 Channel Register Settings During Dual Address Transfer” for more information. Figure 8.4.7 DMA Source Address Increment Register |
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