TMPR4925 datasheet(308/590 Pages) TOSHIBA

308 / 590 page

Chapter 10 PCI Controller

10-46

10.4.20 P2G Interrupt Mask Register (P2GMASK)

0xD098

Reserved

: Type

: Initial value

321

Reserved

PMSCIE PERRIE

GBEIE

R/W

R/W : Type

: Initial value

Bits

Mnemonic

Field Name

Description

31:3



Reserved



PMSCIE

Power

Management

State Change

Interrupt Enable

Power Management State Change Interrupt Enable (Initial value: 0, R/W)

Generates an interrupt when the PowerState field of the Power Management Register

(PMCSR) is rewritten.

1: Generates an interrupt.

0: Does not generate an interrupt.

PERRIE

PERR* Detect

Interrupt Enable

PERR* Interrupt Enable (Initial value: 0, R/W)

This bit generates an interrupt when the Parity Error signal (PERR*) is asserted.

1: Generates an interrupt.

0: Does not generate an interrupt.

GBEIE

G-Bus Bus Error

Detect Interrupt

Enable

G-Bus Bus Error Interrupt Enable (Initial value: 0, R/W)

This bit generates an interrupt when a Bus Error is asserted while the PCI Controller

is the G-Bus Master. (Target cycle to G-Bus)

1: Generates an interrupt.

0: Does not generate an interrupt.

Figure 10.4.20 P2G Interrupt Mask Register

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