SC28L202 datasheet(16/77 Pages) PHILIPS

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Philips Semiconductors

Objective specification

SC28L202

Dual UART

2000 Feb 10

general–purpose output port, the output port pins drive inverse logic

levels of the individual bits in the Output Port Register (OPR). The

OPR register is set and reset by writing to the SOPR and ROPR

addresses. (See the description of the SOPR and ROPR registers).

The output pins will drive the same data polarity of the OPR

registers. The I/OPCR (or the OPCR) register conditions these

output pins to be controlled by the OPR or by other signals in the

chip. Output ports are driven high on hardware reset.

UART Operation

Receiver and Transmitter

The Dual UART has two full duplex asynchronous

receiver/transmitters. The operating frequency for the receiver and

transmitter can be selected independently from the baud rate

generator, the counter, or from an external input. Registers that are

central to basic full–duplex operation are the mode registers (MR0,

MR1 and MR2), the clock select registers (RxCSR and TxCSR), the

command register (CR), the status register (SR), the transmit

holding register (TxFIFO), the receive holding register (RxFIFO),

interrupt status register (ISR) and interrupt mask register (IMR).

MR3 does not exist in 92 mode. MR3 is used in the control of the

intelligent operations of the L202.

Transmitter Status Bits

The SR (Status Register, one per UART) contains two bits that show

the condition of the transmitter FIFO. These bits are TxRDY and Tx

Idle. TxRDY means the TxFIFO has space available for one or more

bytes; Tx Idle means The TxFIFO is completely empty and the last

stop bit has been completed – the transmitter is underrun. Tx Idle

can not be active without TxRDY also being active. These two bits

will go active upon initial enabling of the transmitter

Transmission resumes and the Tx Idle bit is cleared when the CPU

loads at least one new character into the TxFIFO. The TxRDY will

not extinguish until the TxFIFO is completely full. The TxRDY bit will

always be active when the transmitter is enabled and there is at

lease one open position in the TxFIFO.

The transmitter is disabled by a hardware reset, a transmitter reset

in the command register or by the transmitter disable bit also in the

command register (CR). The transmitter must be explicitly enabled

via the CR before transmission can begin. Note that characters

cannot be loaded into the TxFIFO while the transmitter is disabled,

hence it is necessary to enable the transmitter and then load the

TxFIFO. It is not possible to load the TxFIFO and then enable the

transmission.

Note the difference between transmitter disable and transmitter

reset.

Either hardware or software may cause the reset action. When reset

the transmitter stops transmission immediately. The transmit data

output will be driven high, transmitter status bits set to zero and any

data remaining in the TxFIFO is effectively discarded.

The transmitter disable is controlled by the Tx Enable bit in the

command register. Setting this bit to zero will not stop the transmitter

immediately but will allow it to complete any tasks presently

underway. It is only when the last character in the TxFIFO and its

stop bit(s) have been transmitted that the transmitter will go to its

disabled state. While the transmitter enable/disable bit in the

command register is at zero the TxFIFO will not accept any more

characters and the Tx Idle and TxRDY bits of the status register set

to zero.

Transmission of ”break”

Transmission of a break character is often needed as a

synchronizing condition in a data stream. The ”break” is defined as a

start bit followed by all zero data bits by a zero parity bit (if parity is

enabled) and a zero in the stop bit position. The forgoing is the

minimum time to define a break. The transmitter can be forced to

send a break (continuous low condition) by issuing a start break

command via the CR. Once the break starts, the TxD output

remains low until the host issues a command to ”stop break” via the

CR or the transmitter is issued a software or hardware reset. In

normal operation the break is usually much longer than one

character time.

1x and 16x modes, Transmitter

The transmitter clocking has two modes: 16x and 1x. Data is always

sent at the 1x rate. However the logic of the transmitter may be

operated with a clock that is 16 times faster than the data rate or at

the same rate as the data i.e. 1x. All clocks selected internally for

the transmitter (and the receiver) will be 16x clocks. Only when an

external clock is selected may the transmitter logic and state

machine operate in the 1x mode. The 1x or 16x clocking makes little

difference in transmitter operation. (This is not true in the receiver)

In the 16X–clock mode the transmitter will recognize a byte in the

TxFIFO within 1/16 to 2/16–bit time and thus begin transmission of

the start bit. In the 1x mode this delay may be up to 2 bit times.

Transmitter FIFO

The FIFO configuration of the as 28L202 is 256 8–bit words.

Interrupt levels may be set to any level within the FIFO size and may

be set differently for each FIFO. Logic associated with the FIFO

encodes the number of empty positions for presentation to the

interrupt arbitration system. The encoding value is the number of

empty positions. Thus, an empty TxFIFO will bid with the value or

255; when full it will not bid at all; one position empty bids with the

value 0. A Full TxFIFO will not bid since no character is available.

Normally TxFIFO will present a bid to the arbitration system

whenever it has one or more empty positions. The Bits of the

TxFIFO Interrupt Level in the MR0(5:4) allow the user to modify this

characteristic so that bidding will not start until one of four levels

(one or more filled, empty, 16 filled, 240 filled, full) have been

reached. As will be shown later this feature may be used to make

moderate improvements in the interrupt service efficiency. A similar

system exists for the Receiver.

Transmitter

The 28L202 is conditioned to transmit data when the transmitter is

enabled through the command register. The transmitter of the

28L202 indicates to the CPU that it is ready to accept a character by

setting the ISR TxRDY bit in the status register. This condition can

be programmed to generate an interrupt request at

I/O4 or IRQN.

When the transmitter is initially enabled the TxRDY and Tx Idle bits

will be set in the status register. When a character is loaded to the

transmit FIFO the Tx Idle bit will be reset. The Tx Idle bit will not set

until the transmit FIFO is empty and the transmit shift register has

finished transmitting the stop bit of the last character written to the

transmit FIFO.

The TxRDY bit is set whenever the transmitter is enabled and the

TxFIFO is not full. Data is transferred from the holding register to

transmit shift register when it is idle or has completed transmission

of the previous character. Characters cannot be loaded into the

TxFIFO while the transmitter is disabled.

The transmitter converts the parallel data from the CPU to a serial

bit stream on the TxD output pin. It automatically sends a start bit

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