EMC2101-R-ACZL-TR datasheet(36/56 Pages) MICROCHIP

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EMC2101

DS20006703A-page 36

 2022 Microchip Technology Inc. and its subsidiaries

5.19

PWM Frequency Register

The PWM Frequency Register determines the final

PWM frequency and “effective resolution” of the PWM

driver. It has no affect on the DAC output resolution.

It is recommended that this register be set at 1Fh for

maximum resolution. See Appendix B: “Advanced

PWM Options” for full operation of the PWM_F

and Duty Cycle.

5.20

PWM Frequency Divide Register

This register holds an alternate PWM Frequency divide

value that can be used instead of the CLK_SEL bit

function. This register can be written at any time,

however unless the CLK_OVR bit is set to a logic ‘1’, it

is not used.

When the CLK_OVR bit is set to a logic ‘1’, the PWM

Frequency Divide Register is used in conjunction with

the PWM Frequency Register to determine the final

PWM frequency that the load will see. When the

CLK_OVR bit is set to a logic ‘0’, the setting of this

effective PWM frequency.

The PWM frequency when the PWM Frequency Divide

EQUATION 5-4:

PWM FREQUENCY REGISTER (ADDRESS 4Dh)

Address

R/W

Default

4Dh

R/W

PWM

Frequency

—

PWM_F[4:0]

17h

PWM FREQUENCY DIVIDE REGISTER (ADDRESS 4Eh)

Address

R/W

Default

4Eh

R/W

PWM

Frequency Divide

PWM_D[7:0]

01h

PWM_D

360k

2 PWM_F



-------------------------------





FREQ

----------------



5806

FREQ

----------------

Where:

PWM_F = The setting of the PWM Frequency

PWM_D = The setting of the PWM Frequency

Divide Register (4Eh)

FREQ = The desired PWM Frequency

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