EMC2101-R-ACZL-TR datasheet(9/56 Pages) MICROCHIP

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DS20006703A-page 9

EMC2101

2.6

Alert Response Address

The ALERT/TACH output can be used as a processor

interrupt or as an SMBus Alert when configured to

operate as an interrupt.

When it detects that the ALERT/TACH pin is asserted,

the host sends the Alert Response Address (ARA) to

the general address of 000_1100b. All devices with

active interrupts will respond with their client address

as shown in Table 2-6.

The EMC2101 responds to the ARA in the following

way when the ALERT/TACH pin is configured as an

Interrupt:

• Send client Address and verify that full client

address was sent (i.e. the SMBus communication

from the device was not prematurely stopped due

to a bus contention event).

• Set the MASK bit to clear the ALERT/TACH pin

only if there are no bits set in the Status Register.

If there are error condition bits set in the Status

be set.

When the ALERT/TACH pin is configured to operate in

Comparator Mode or as a TACH input (see

Section 4.4.1 “ALERT/TACH as a Temperature

Comparator”), it does not respond to the ARA com-

mand. Additionally, the EMC2101 does not respond to

the ARA command if the ALERT/TACH pin is not

asserted.

2.7

SMBus Address

The EMC2101 is addressed on the SMBus as

100_1100b.

Attempting to communicate with the EMC2101 SMBus

interface with an invalid client address or invalid proto-

col results in no response from the device and does not

affect its register contents.

2.8

SMBus Timeout

The EMC2101 includes an SMBus time-out feature.

Following a 25 ms period of inactivity on the SMBus,

the device times-out and resets the SMBus interface.

2.9

Programming from EEPROM

The EMC2101-R acts as a simple SMBus Host to read

data from a connected EEPROM using the following

procedure:

After power-up the EMC2101-R waits for 10 ms

with the SMDATA and SMCLK pins tri-stated.

Once the wait period has elapsed, the

EMC2101-R sends a START signal followed by

the 7 bit client address 101_0000b followed by a

‘1b’ and waits for an ACK signal from the

EEPROM.

When the EEPROM sends the ACK signal, the

EMC2101-R sends a second Start signal and

continues sending the Block Read Command

(see Table 2-7) to the same client address. It

reads 256 data bytes from the EEPROM send-

ing an ACK between each data byte. When 256

data bytes have been received, it sends a NACK

signal followed by a STOP bit.

Resets the device as an SMBus Client.

If the EMC2101-R does not receive an acknowledge bit

from the EEPROM, then the following occurs:

The ALERT/TACH pin will be asserted and will

remain asserted until a Host device initiates

communication with the EMC2101 and reads

the Status Register at offset 0x02. The

ALERT/TACH pin will be deasserted after a sin-

gle Status Register read (i.e. it is not sticky).

The EMC2101-R will reset its SMBus protocol

as a client interface and start operating from the

default conditions.

TABLE 2-6:

ALERT RESPONSE ADDRESS PROTOCOL

START

ALERT Response Address

ACK

Device Address

NACK

STOP

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