ST72324BJ2 datasheet(113/188 Pages) STMICROELECTRONICS

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ST72324B

On-chip peripherals

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Even parity

The parity bit is calculated to obtain an even number of ‘1’s inside the frame made of the 7 or

8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit, for example,

data = 00110101; 4 bits set => Parity bit will be 0 if Even parity is selected (PS bit = 0).

Odd parity

The parity bit is calculated to obtain an odd number of ‘1’s inside the frame made of the 7 or

8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit, for example,

data = 00110101; 4 bits set => Parity bit will be 1 if Odd parity is selected (PS bit = 1).

Transmission mode

If the PCE bit is set then the MSB bit of the data written in the data register is not transmitted

but is changed by the parity bit.

Reception mode

If the PCE bit is set then the interface checks if the received data byte has an even number

of ‘1’s if even parity is selected (PS = 0) or an odd number of ‘1’s if odd parity is selected

(PS = 1). If the parity check fails, the PE flag is set in the SCISR register and an interrupt is

generated if PIE is set in the SCICR1 register.

SCI clock tolerance

During reception, each bit is sampled 16 times. The majority of the 8th, 9th and 10th

samples is considered as the bit value. For a valid bit detection, all the three samples should

have the same value otherwise the noise flag (NF) is set. For example: If the 8th, 9th and

10th samples are 0, 1 and 1 respectively, then the bit value will be ‘1’, but the Noise flag bit

is set because the three samples values are not the same.

Consequently, the bit length must be long enough so that the 8th, 9th and 10th samples

have the desired bit value. This means the clock frequency should not vary more than 6/16

(37.5%) within one bit. The sampling clock is resynchronized at each start bit, so that when

receiving 10 bits (one start bit, 1 data byte, 1 stop bit), the clock deviation must not exceed

3.75%.

Note:

The internal sampling clock of the microcontroller samples the pin value on every falling

edge. Therefore, the internal sampling clock and the time the application expects the

sampling to take place may be out of sync. For example: If the baud rate is 15.625 kbaud (bit

length is 64µs), then the 8th, 9th and 10th samples will be at 28µs, 32µs and 36µs

respectively (the first sample starting ideally at 0µs). But if the falling edge of the internal

clock occurs just before the pin value changes, the samples would then be out of sync by

~4µs. This means the entire bit length must be at least 40µs (36µs for the 10th sample + 4µs

for synchronization with the internal sampling clock).

ST72324BJ2 Datasheet(PDF) 113 Page - STMicroelectronics