ST72324BJ2 datasheet(116/188 Pages) STMICROELECTRONICS

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On-chip peripherals

ST72324B

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6TC

Transmission Complete

This bit is set by hardware when transmission of a frame containing data is complete.

An interrupt is generated if TCIE = 1 in the SCICR2 register. It is cleared by a

software sequence (an access to the SCISR register followed by a write to the

SCIDR register).

0: Transmission is not complete

1: Transmission is complete

Note: TC is not set after the transmission of a Preamble or a Break.

RDRF

Received Data Ready Flag

This bit is set by hardware when the content of the RDR register has been

transferred to the SCIDR register. An interrupt is generated if RIE = 1 in the SCICR2

followed by a read to the SCIDR register).

0: Data is not received

1: Received data is ready to be read

4IDLE

Idle line detect

This bit is set by hardware when a Idle Line is detected. An interrupt is generated if

the ILIE = 1 in the SCICR2 register. It is cleared by a software sequence (an access

to the SCISR register followed by a read to the SCIDR register).

0: No idle line is detected

1: Idle line is detected

Note: The IDLE bit is not reset until the RDRF bit has itself been set (that is, a new

idle line occurs).

3OR

Overrun error

This bit is set by hardware when the word currently being received in the shift register

is ready to be transferred into the RDR register while RDRF = 1. An interrupt is

generated if RIE = 1 in the SCICR2 register. It is cleared by a software sequence (an

access to the SCISR register followed by a read to the SCIDR register).

0: No overrun error

1: Overrun error is detected

Note: When this bit is set RDR register content is not lost but the shift register is

overwritten.

2NF

Noise Flag

This bit is set by hardware when noise is detected on a received frame. It is cleared

by a software sequence (an access to the SCISR register followed by a read to the

SCIDR register).

0: No noise is detected

1: Noise is detected

Note: This bit does not generate interrupt as it appears at the same time as the

RDRF bit which itself generates an interrupt.

1FE

Framing Error

This bit is set by hardware when a desynchronization, excessive noise or a break

character is detected. It is cleared by a software sequence (an access to the SCISR

0: No framing error is detected

1: Framing error or break character is detected

Note: This bit does not generate interrupt as it appears at the same time as the

RDRF bit which itself generates an interrupt. If the word currently being transferred

causes both Frame Error and Overrun error, it is transferred and only the OR bit will

be set.

Table 61.

SCISR register description (continued)

Bit

Name

Function

ST72324BJ2 Datasheet(PDF) 116 Page - STMicroelectronics

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