HT9480 datasheet(6/47 Pages) HOLTEK

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HT9480

Rev. 1.20

July 31, 2002

T 1

T 2

T 3

T 4

T 1

T 2

T 3

T 4

T 1

T 2

T 3

T 4

. e t c h I N S T ( P C )

E x e c u t e I N S T ( P C - 1 )

. e t c h I N S T ( P C + 1 )

E x e c u t e I N S T ( P C )

. e t c h I N S T ( P C + 2 )

E x e c u t e I N S T ( P C + 1 )

P C

P C + 1

P C + 2

S y s t e m C l o c k

O S C 2 ( R C o n l y )

P C

Execution flow

Functional Description

Execution flow

The HT9480 system clock can be derived from either a

crystal or an RC oscillator. It is internally divided into four

non-overlapping clocks denoted by P1, P2, P3, and P4.

Each instruction cycle consists of T1 to T4.

Instruction fetching and execution are pipelined in such

a way that a fetch takes an instruction cycle while de-

coding and execution take the next instruction cycle.

The pipelining scheme causes each instruction to effec-

tively execute within a cycle. If an instruction changes

the content of the program counter two cycles are re-

quired to complete the instruction.

Program counter

- PC

The program counter (PC) is 13-bit wide and controls

the program ROM instruction sequence execution. The

contents of the PC can specify a of maximum 8192 ad-

dresses.

The PC value is incremented by one after a program

memory word is accessed in order to fetch an instruction

code. The PC then points to a memory word with the

next instruction code.

The PC loads the address corresponding to each in-

struction and then manipulates program transfer while

executing a jump instruction, conditional skip execution,

loading a PCL, a register, a subroutine call, an initial re-

set, an internal interrupt, an external interrupt, or return-

ing from a subroutine.

The conditional skip is activated by instructions. Once

the condition is satisfied, the next instruction, fetched

during the current instruction execution, is discarded,

and a dummy cycle is replaced to get a proper instruc-

tion. Otherwise it proceeds with the following instruction.

The low byte of the PC (PCL) is a readable and writable

short jump. The destination is within 256 locations.

If a control transfer takes place, an additional dummy

cycle is required.

Mode

Program Counter

*12

*11

*10

Initial Reset

0000000000000

Data Ready Interrupt and

Battery Fail Interrupt

0000000000100

Programmable Timer Interrupt

0000000001000

Timer/event Counter Interrupt

0000000001100

Skip

PC+2

Loading PCL

*12

*11

*10

Jump, Call Branch

#12

#11

#10

Return from Subroutine

S12

S11

S10

Program counter

Note: *12~*0: Program counter bits

S12~S0: Stack register bits

#12~#0: Instruction code bits

@7~@0: PCL bits

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