HT9480 datasheet(10/47 Pages) HOLTEK

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HT9480

Rev. 1.20

July 31, 2002

Interrupts

The HT9480 provides an internal programmable timer

interrupt, an internal data ready interrupt, timer/event

counter interrupt, and a battery fail interrupt. The inter-

nal data ready interrupt and the battery fail interrupt em-

ploy the same jump location (04H). The interrupt control

not only the enable/disable status but also the interrupt

request flags.

Once an interrupt subroutine is serviced, the other inter-

rupts will all be blocked (by clearing the EMI bit). This

scheme may prevent any further interrupt nesting. Other

interrupt requests may occur during this interval, but

only the interrupt request flag is recorded. If a certain in-

terrupt requires servicing within the service routine, the

EMI bit and the corresponding bit of the INTC register

may be set to permit interrupt nesting. When the stack is

full, the interrupt request will not be acknowledged even

if the related interrupt is enabled, until the SP is decre-

mented. If immediate service is desired, the stack

should be prevented from becoming full.

All of these interrupts can support the wake-up function.

As an interrupt is serviced, a control transfer occurs by

pushing the contents of the PC onto the stack, followed

by a branch to a subroutine at the specified location in

the program memory. Only the contents of the PC is

pushed onto the stack. If the contents of the register or

of the status register (STATUS) is altered by the inter-

rupt service program which corrupts the desired control

sequence, the contents should be saved in advance.

The data ready interrupt and battery fail interrupt share

the same subroutine call location 04H. Checking the

battery fail interrupt bit (BF;bit 4 of 1EH) and the data

ready interrupt bit (DR; bit 7 of 1EH) can determine

which kind of interrupt has occurred. The value of

1EH-bit 7 DR is cleared

²0² by the decoder data ready

interrupt signal, and is set to

²1² when the MCU sets this

bit high. Both interrupt bits are active low.

The data ready interrupt is generated by the pager de-

coder after a valid call is received, and is initialized by

setting the data ready interrupt request flag (EIF; bit 4 of

INTC) and the data ready interrupt bit (DR; bit 7 of 1EH).

Labels

Bits

Function

C is set if the operation results in a carry out in addition or if a borrow does not take place in sub-

traction; otherwise C is cleared. C is also affected by a rotate through carry instructions.

AC is set if the operation results in a carry out of the low nibbles in addition or if a borrow from the

high nibble into the low nibble does not take place in subtraction; otherwise AC is cleared.

Z is set if the result of an arithmetic or a logic operation is zero; otherwise Z is cleared.

OV is set if the operation results in a carry into the high-order bit but not a carry out of the

high-order bit, or vice versa; otherwise OV is cleared.

PD is cleared during power up, and set by a

²HALT² instruction.

TO is cleared during power up or by a

²CLR WDT² instruction and a ²HALT² instruction. TO is

set by a current timer time-out.

Undefined, read as

²0²

Undefined, read as

²0²

STATUS register

Bit No.

Label

Function

INTC

(0BH)

EMI

Controls the master (global) interrupt (1=enabled; 0=disabled)

EEI

Controls the data ready and battery fail interrupts (1=enabled; 0=disabled)

ET0I

Controls the programmable timer interrupt (1=enabled; 0=disabled)

ET1I

Controls the timer/event counter interrupt (1=enabled, 0=disabled)

EIF

Internal data ready and battery fail interrupt request flag (1=active; 0=inactive)

T0F

Internal programmable timer interrupt request flag (1=active; 0=inactive)

T1F

Timer/event counter request flag (1=active; 0=inactive)

Unused bit, read as

²0²

INTC register

HT9480 Datasheet(PDF) 10 Page - Holtek Semiconductor Inc

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