HT9480

Rev. 1.20

20

July 31, 2002

Decoder interface

The HT9480 has two interfaces available. One is the

pager control address (1EH), which controls the opera-

tion and configuration of the decoder. The other is the

pager data address (1FH), which places the message

data of calls in the parallel mode.

The decoder control address (1EH) contains a data

ready flag (DR), a battery low flag (BL), an out of

range flag (OR), a battery fail flag (BF), a decoder

standby flag (STB), a call termination indication flag

(CT), a decoder software reset (RES), and a decoder

on/off control bit (ON). It not only records the status in-

formation but controls the operation of the decoder.

Any data written to the decoder control address can-

not change the OR,BF, STB and CT flags.

If the status of the battery fail (BF) changes from

²1² to

²0², the following conditions occur.

of the data ready interrupt flag is

²1².

and no data is transmitted if the value of the data ready

interrupt flag is

²0².

On the other hand, if the status of the battery fail (BF)

changes from

²0² to ²1², the internal node PA.7 of the

pager controller will supply a wake-up function.

After the decoder asserts the data transfer request,

the data ready interrupt is generated and the DR bit

(bit 7 of 1EH) is cleared low; then the data ready inter-

rupt subroutine runs to process the call data and resets

the DR bit high.

C T

M C U ( I N T )

P a g e r D e c o d e r

B S 3

B A L

D I

R .

C K T .

D e c o d e r d a t a o u t p u t

1 E H

1 . H

D a t a R e a d y i n t e r r u p t

B i t 0

B i t 1

B i t 2

B i t 3

B i t 4

B i t 5

B i t 6

B L

O R

O N

B S 1

B S 2

B i t 7

D R

T h e v a l u e o f 1 E H - b i t 4 B . i s d e p e n d e n t o n t h e B A . p i n .

B .

B A . ( B a t t e r y f a i l i n t e r r u p t )

M C U P A 7

( w a k e u p )

S T B

N o t e s : T h e v a l u e o f 1 E H - b i t 3 S T B i s s e t w h e n d e c o d e r e n t e r e s t h e s t a n d b y m o d e a n d c l e a r e d w h e n d e c o d e r e n t e r s t h e O N m o d e .

V I H = 1 . 2 V

V I L = 0 . 9 V

R E S

D e b o u n c e

C i r c u i t

B i t 0

B i t 1

B i t 2

B i t 3

B i t 4

B i t 5

B i t 6

B i t 7

P a g e r s y s t e m c l k

1

T h e v a l u e o f 1 E H - b i t 5 O R i s a l w a y s c h a n g e d b y o u t o f r a n g e s i g n a l .

T h e v a l u e o f 1 E H - b i t 6 B L i s c l e a r e d " 0 " b y t h e d e c o d e r B a t t e r y L o w s i g n a l a n d s e t " 1 " w h e n M C U s e t s t h i s b i t h i g h .

T h e v a l u e o f 1 E H - b i t 7 D R i s c l e a r e d " 0 " b y t h e d e c o d e r D a t a - R e a d y i n t e r r u p t s i g n a l a n d s e t " 1 " w h e n M C U s e t s t h i s b i t h i g h .

T h e v a l u e o f 1 E H - b i t 2 C T i s c l e a r e d " 0 " w h e n e n d o f m e s s a g e w o r d a n d s e t " 1 " d u r i n g r e c e i v i n g m e s s a g e w o r d .

Decoder interface