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MNSC140CORE Datasheet(PDF) 53 Page - Freescale Semiconductor, Inc |
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MNSC140CORE Datasheet(HTML) 53 Page - Freescale Semiconductor, Inc |
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53 / 88 page  AC Timings MSC8122 Technical Data, Rev. 13 Freescale Semiconductor 2-19 2.5.6.2 DSI Synchronous Mode Table 2-18. DSI Inputs in Synchronous Mode No. Characteristic Expression 1.1 V Core 1.2 V Core Units Min Max Min Max 120 HCLKIN cycle time1,2 HTC 10.0 55.6 10.0 55.6 ns 121 HCLKIN high pulse width (0.5 ± 0.1) × HTC 4.0 33.3 4.0 33.3 ns 122 HCLKIN low pulse width (0.5 ± 0.1) × HTC 4.0 33.3 4.0 33.3 ns 123 HA[11–29] inputs set-up time — 1.2 — 1.2 — ns 124 HD[0–63] inputs set-up time — 0.6 — 0.4 — ns 125 HCID[0–4] inputs set-up time — 1.3 — 1.3 — ns 126 All other inputs set-up time — 1.2 — 1.2 — ns 127 All inputs hold time — 1.5 — 1.5 — ns Notes: 1. Values are based on a frequency range of 18–100 MHz. 2. Refer to Table 2-6 for HCLKIN frequency limits. Table 2-19. DSI Outputs in Synchronous Mode No. Characteristic 1.1 V Core 1.2 V Core Units Min Max Min Max 128 HCLKIN high to HD[0–63] output active 2.0 — 2.0 — ns 129 HCLKIN high to HD[0–63] output valid — 7.6 — 6.3 ns 130 HD[0–63] output hold time 1.7 — 1.7 — ns 131 HCLKIN high to HD[0–63] output high impedance — 8.3 — 7.6 ns 132 HCLKIN high to HTA output active 2.2 — 2.0 — ns 133 HCLKIN high to HTA output valid — 7.4 — 5.9 ns 134 HTA output hold time 1.7 — 1.7 — ns 135 HCLKIN high to HTA high impedance — 7.5 — 6.3 ns Figure 2-11. DSI Synchronous Mode Signals Timing Diagram HCLKIN HA[11–29] input signals All other input signals HD[0–63] output signals HTA output signal HD[0–63] input signals 120 127 123 126 127 122 121 131 130 129 128 133 135 134 132 HCID[0–4] input signals 125 127 127 124 |
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