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MNSC140CORE Datasheet(PDF) 60 Page - Freescale Semiconductor, Inc |
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MNSC140CORE Datasheet(HTML) 60 Page - Freescale Semiconductor, Inc |
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60 / 88 page  MSC8122 Technical Data, Rev. 13 2-26 Freescale Semiconductor Specifications 704 Boundary scan input data set-up time 5.0 — ns 705 Boundary scan input data hold time 20.0 — ns 706 TCK low to output data valid 0.0 30.0 ns 707 TCK low to output high impedance 0.0 30.0 ns 708 TMS, TDI data set-up time 5.0 — ns 709 TMS, TDI data hold time 20.0 — ns 710 TCK low to TDO data valid 0.0 20.0 ns 711 TCK low to TDO high impedance 0.0 20.0 ns 712 TRST assert time 100.0 — ns 713 TRST set-up time to TCK low 30.0 — ns Note: All timings apply to OnCE module data transfers as well as any other transfers via the JTAG port. Figure 2-23. Test Clock Input Timing Diagram Figure 2-24. Boundary Scan (JTAG) Timing Diagram Table 2-29. JTAG Timing (Continued) No. Characteristics All frequencies Unit Min Max TCK (Input) VM VM VIH VIL 701 702 703 703 TCK (Input) Data Inputs Data Outputs Data Outputs VIH VIL Input Data Valid Output Data Valid 705 704 706 707 |
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