MPC8280 datasheet(356/1386 Pages) FREESCALE

356 / 1386 page

PCI Bridge

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

9-48

Freescale Semiconductor

Figure 9-35. PCI Bus Command Register

9.11.2.4

PCI Bus Status Register

The PCI bus status register, shown in Figure 9-36, is used to record status information for PCI bus-related

events. Only 2-byte accesses to address offset 0x06 are allowed.

Field

—

FB-B

SERR

—

PERRR

—

MWI

MEM

I/O

Reset

0000_0000_0000_0000

R/W

Addr

0x04

Table 9-22. PCI Bus Command Register Description

Bits

Name

Description

15–10

—

Reserved, should be cleared.

Fast back-to-back

Hardwired to 0, indicating that the PCI bridge as a master does not run fast

back-to-back transactions.

SERR

Controls the SERR driver of the PCI bridge. This bit (and bit 6) must be set to report

address parity errors.

0 Disables the SERR driver

1 Enables the SERR driver

—

Reserved, should be cleared.

Parity error response

Controls whether the PCI bridge responds to parity errors on the PCI bus.

0 Parity errors are ignored and normal operation continues.

1 Action is taken on a parity error.

—

Reserved, should be cleared.

Memory-write-and-

invalidate

Hardwired to 0, indicating that the PCI bridge acting as a master does not generate

the memory-write-and-invalidate command. The PCI bridge generates a

memory-write command instead.

Special-cycles

Hardwired to 0, indicating that the PCI bridge as a target ignores all special-cycle

commands.

Bus master

Controls whether the PCI bridge can act as a master on the PCI bus. This bit is

cleared if the PCI bridge is powered-up as an agent device and is set if it is

powered-up as a host bridge device.

0 Disables the ability to generate PCI accesses. In host bridge mode, read

transactions return undefined data and write transactions lose data. In agent

mode, transactions are held until this bit is enabled.

1 Enables the PCI bridge to behave as a PCI bus master

Memory space

Controls whether the PCI bridge as a target responds to memory accesses.

0 The PCI bridge does not respond to PCI memory space accesses.

1 The PCI bridge responds to PCI memory space accesses.

I/O space

Hardwired to 0, indicating that the PCI bridge as a target does not respond to PCI

I/O space accesses.

MPC8280 Datasheet(PDF) 356 Page - Freescale Semiconductor, Inc

MPC8280 Datasheet(HTML) 356 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL