MPC8280 datasheet(357/1386 Pages) FREESCALE

357 / 1386 page

PCI Bridge

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

9-49

Reads to this register behave normally. Writes are slightly different in that bits can be cleared, but not set.

A bit is cleared whenever the register is written, and the data in the corresponding bit location is set. For

example, to clear bit 14 and not affect any other bits in the register, write the value

0b0100_0000_0000_0000 to the register.

Figure 9-36. PCI Bus Status Register

Table 9-23 describes the PCI bus status register fields.

Field DPERR SSERR

RM-A

RT-A

ST-A

DEVSEL_T

DPD

FB-BC

—

66MHzC

—

Reset

0000_0000_1011_0000

R/W

Addr

0x06

Table 9-23. PCI Bus Status Register Description

Bits

Name

Description

Detected parity error

Set whenever the PCI bridge detects a parity error on the PCI bus, even if parity

error handling is disabled (as controlled by bit 6 in the PCI bus command register).

Signaled system error

Set whenever the PCI bridge asserts SERR on the PCI bus.

Received master-abort Set whenever the PCI bridge, acting as the PCI master on the PCI bus, terminates

a transaction (except for a special-cycle) using master-abort.

Received target-abort

Set whenever a PCI bridge-initiated transaction on the PCI bus is terminated by

a target-abort.

Signaled target-abort

Set whenever the PCI bridge, acting as the PCI target on the PCI bus, issues a

target-abort to a PCI master.

10–9

DEVSEL timing

Hardwired to 0b00, indicating that the PCI bridge uses fast device-select timing

on the PCI bus.

Data parity detected

Set upon detecting a data parity error on the PCI bus. Three conditions must be

met for this bit to be set:

• The PCI bridge detects a parity error.

• The PCI bridge is acting as the bus master for the operation in which the error

occurred.

• Bit 6 in the PCI bus command register is set.

Fast back-to-back

capable

Hardwired to 1, indicating that the PCI bridge as a target is capable of accepting

fast back-to-back transactions.

—

Reserved, should be cleared.

66-MHz capable

This bit is read-only and indicates that the PCI bridge is capable of 66-MHz PCI

bus operation on the PCI bus.

Capabilities List

Hardwired to 1, indicating that the PCI bridge implements new capabilities on the

PCI bus.

3–0

—

Reserved, should be cleared.

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