MPC8280 datasheet(408/1386 Pages) FREESCALE

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PCI Bridge

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

9-100

Freescale Semiconductor

9.14.1.3

PCI Interface

The PCI bridge supports the error detection and reporting mechanism as specified in the PCI Local Bus

Specification, Revision 2.2. The PCI bridge detects master and target abort errors, address parity errors,

received SERR, and master and target PERR errors. In these cases, the appropriate bit is set in the ESR,

and the address, data and control information about the transaction is loaded in the PCI error address

capture register (PCI_EACR), the PCI data capture register (PCI_EDCR) and the PCI error control capture

9.14.1.3.1

Address Parity Error

If the PCI bridge is acting as a PCI master and the target detects and reports (by asserting SERR) a PCI

address parity error, the PCI bridge sets bit 5 of the ESR and sets the detected parity error bit (bit 15) in

the PCI status register. This setting of bit 15 is independent of the settings in the PCI command register.

If the PCI bridge is acting as a PCI target and detects a PCI address parity error, the PCI interface of the

PCI bridge sets the status bit in the PCI status register (bit 15) and bit 0 of the ESR. If bits 6 and 8 of the

PCI command register are set, the PCI bridge reports the address parity error by asserting SERR to the

master (two clocks after the address phase) and sets bit 14 of the PCI status register.

9.14.1.3.2

Data Parity Error

If the PCI bridge is acting as a PCI master and a write data parity error is signaled by the target asserting

PERR, the PCI bridge sets bit 8 of the PCI status register if the parity error response bit (bit 6) in the PCI

command Register is set. The PCI bridge sets bit 7 of the error status register (refer to Section 9.11.1.9,

“Error Status Register (ESR)”), regardless of the configuration of the PCI command register.

If the PCI bridge is acting as a PCI master and a read data parity error occurs, the PCI bridge sets bit 8 of

the PCI status register if the parity error response bit (bit 6) in the PCI command register is set. The PCI

bridge sets bit 2 of the error status register. If the PCI command register of the PCI bridge is programmed

to respond to parity errors (bit 6 of the PCI command register is set) the PCI bridge reports the error to the

PCI target by asserting PERR and tries to complete the command if possible. The PCI bridge also sets bit

15 of the PCI status register regardless of the value of the parity error response bit (bit 6) in the PCI

command register.

If the PCI bridge is acting as a PCI target when the write data parity error occurs, the PCI bridge sets bit

15 of the PCI status register and bit 1 of the error status register (ESR). The setting of these bits is

independent of the settings in the PCI command register. If bit 6 of the PCI command Register is set, the

PCI bridge asserts PERR. When the data has all been transferred, the PCI bridge completes the operation

but ignores the data.

If the PCI bridge is acting as a PCI target when the master asserts PERR, the PCI bridge sets bit 6 of ESR

(refer to Section 9.11.1.9, “Error Status Register (ESR)”), regardless of the configuration of the PCI

command register.

9.14.1.3.3

Master-Abort Transaction Termination

If the PCI bridge, acting as a master, initiates a PCI bus transaction (excluding special-cycle transactions)

but there is no response from any PCI agent (DEVSEL has not been asserted within five PCI bus clocks

MPC8280 Datasheet(PDF) 408 Page - Freescale Semiconductor, Inc

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