MPC8280 datasheet(404/1386 Pages) FREESCALE

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PCI Bridge

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

9-96

Freescale Semiconductor

Table 9-72 describes DMANDARx fields.

9.13.2

DMA Segment Descriptors

DMA segment descriptors contain the source and destination addresses of the data segment, the segment

byte count, and a link to the next descriptor. Segment descriptors are built on cache-line (32-byte)

boundaries in either 60x or PCI memory and are linked together into chains using the

next-descriptor-address field.

Application software initializes the current descriptor address register (DMACDARx) to point to the first

descriptor in the chain. For each descriptor in the chain, the DMA controller starts a new DMA transfer

with the control parameters specified by the descriptor. The DMA controller traverses the descriptor chain

until reaching the last descriptor (with its EOTD bit set).

Table 9-72. DMANDAR

x Field Descriptions

Bit

Name

Description

31–5

NDA

Next descriptor address. Contains the next descriptor address of the segment descriptor

in memory. It must be aligned on an 8-word (32-byte) boundary.

NDSNEN

Next descriptor snoop enable. When set will allow snooping on DMA transactions.

NDEOSIE

Next descriptor end-of-segment interrupt enable. When set will generate an interrupt at

the end of this DMA transfer.

2–1

—

Reserved, should be cleared.

EOTD

End-of-transfer descriptor. When set indicates that this descriptor is the last one to be

executed.

Table 9-73. DMA Segment Descriptor Fields

Descriptor Field

Description

Source address

Contains the source address of the DMA transfer. After the DMA controller reads the

descriptor from memory, this field will be loaded into the source address register. For the bit

definition, refer to Section 9.13.1.6.4, “DMA Source Address Registers 0–3 (DMASARx).”

Destination address

Contains the destination address of the DMA transfer. After the DMA controller reads the

descriptor from memory, this field will be loaded into the destination address register. For the

bit definition, refer to Section 9.13.1.6.5, “DMA Destination Address Registers 0–3

(DMADARx).”

Next descriptor address Points to the next descriptor in memory. After the DMA controller reads the descriptor from

memory, this field will be loaded into the next descriptor address register. For the bit definition,

refer to Section 9.13.1.6.7, “DMA Next Descriptor Address Registers 0–3 (DMANDARx).”

Byte count

Contains the number of bytes to transfer. After the DMA controller reads the descriptor from

memory, this field will be loaded into the byte count register. For the bit definition, refer to

Section 9.13.1.6.6, “DMA Byte Count Registers 0–3 (DMABCRx).”

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