MPC8280 datasheet(409/1386 Pages) FREESCALE

409 / 1386 page

PCI Bridge

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

9-101

from the start of the address phase), the PCI bridge terminates the transaction with a master-abort and sets

the master-abort flag (bit 13) in the PCI status register and bit 3 in the ESR.

In the case of no response for a PCI read configuration transaction, the PCI bridge terminates the

transaction with a master-abort, but will return data of all ones and will not assert a machine check. This

kind of termination enables the host CPU to perform a PCI device scan without having to know in advance

if a particular PCI slot is populated or empty. The software still needs to mask the PCI_NO_RSP bit in the

error mask register (refer to Section 9.11.1.10, “Error Mask Register (EMR)”). Any other type of

transaction that is terminated with a master-abort results in a machine check interrupt.

9.14.1.3.4

Target-Abort Error

If a PCI transaction initiated by the PCI bridge is terminated by target-abort, the PCI bridge sets the

received target-abort flag (bit 12) of the PCI status register and bit 4 of the error status register (refer to

Section 9.11.1.9, “Error Status Register (ESR)”). Note that data transferred in a target-aborted transaction

may be corrupt.

9.14.1.3.5

NMI

This signal is captured in bit 11 of the ESR (refer to Section 9.11.1.9, “Error Status Register (ESR)”). It

indicates that an error has occurred on the 60x bus in a transaction that was originally initiated by the PCI

bridge.

9.14.1.4

Embedded Utilities

Embedded utilities errors are errors detected in the I2O interface. Embedded utilities errors are limited to

queue overflows in the I2O outbound free queue and the inbound post queue.

9.14.1.4.1

Outbound Free Queue Overflow

If the PCI bridge detects an I2O outbound free queue overflow, it sets bit 8 of the error status register (refer

to Section 9.11.1.9, “Error Status Register (ESR)”) and freezes all I2O state information.

9.14.1.4.2

Inbound Post Queue Overflow

If the PCI bridge detects an I2O inbound post queue overflow, it sets bit 9 of the error status register (refer

to Section 9.11.1.9, “Error Status Register (ESR)”) and freezes all I2O state information.

9.14.1.4.3

Inbound DoorBell Machine Check

If an external PCI master writes the inbound doorbell register such that the most significant bit is set, then

bit 12 of ESR (refer to Section 9.11.1.9, “Error Status Register (ESR)”) is set and a machine check is

asserted to the local processor.

MPC8280 Datasheet(PDF) 409 Page - Freescale Semiconductor, Inc