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MPC8280 Datasheet(PDF) 413 Page - Freescale Semiconductor, Inc |
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MPC8280 Datasheet(HTML) 413 Page - Freescale Semiconductor, Inc |
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413 / 1386 page  Clocks and Power Control MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 10-3 Figure 10-1. MPC8280 System Clock Architecture CLKIN1 MAIN_CLK (= 2 X CPM_CLK) X (SCMR[PLLMF] + 1) BUS_CLK CORE_CLK Main PLL for CPM Clocks ÷ 2 ÷ (SCMR[BUSDF] + 1) CPM_CLK BUS_CLK2 SCC_CLK BRG_CLK General-purpose divider ÷ (SCCR[PCIDF] + 1) PCI_CLK1 Core Notes: 1 In PCI agent mode, CLKIN = PCI_CLK. Refer to Section 10.1.6, “PCI Bridge as an Agent Operating from the PCI System Clock.” 2 BUS_CLK = CLKIN. 3 The core PLL multiplication is set through SCMR[CORECNF] as described in Table 10-3. 4 SCMR is a read-only register. Its value is determined during power-on reset (PORESET). Refer to Section 10.5, “System Clock Mode Register (SCMR).” SCMR[CORECNF]3 ÷ 22(SCCR[DFBRG] + 1) General-purpose divider General-purpose divider General-purpose divider General-purpose divider CORE PLL CPM PLL ÷ 4 |
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