MPC8280 datasheet(415/1386 Pages) FREESCALE

415 / 1386 page

Clocks and Power Control

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

10-5

Figure 10-3. PCI Bridge as a Host, Generating the PCI System Clock

10.2

External Clock Inputs

The input clock source to the PLL is an external clock oscillator at the bus frequency. The PLL skew

elimination between the CLOCKIN pin and the internal bus clock is guaranteed.

10.3

PLL Pins

Table 10-1 shows the dedicated PLL pins.

Figure 10-4. PLL Filtering Circuit

Table 10-1. Dedicated PLL Pins

Signal

Description

VCCSYN1 Drain Voltage—Analog VDD dedicated to core analog PLL circuits. To ensure core clock stability, filter

the power to the VCCSYN1 input with a circuit similar to the one in “PLL Filtering Circuit” Figure. To filter

as much noise as possible, place the circuit as close as possible to VCCSYN1. The 0.1-µF capacitor

should be closest to VCCSYN1, followed by the 10-µF capacitor, and finally the 10-

Ω resistor to Vdd.

These traces should be kept short and direct.

VCCSYN

Drain Voltage—Analog VDD dedicated to analog main PLL circuits. To ensure internal clock stability,

filter the power to the VCCSYN input with a circuit similar to the one in “PLL Filtering Circuit” Figure. To

filter as much noise as possible, place the circuit should as close as possible to VCCSYN. The 0.1-µF

capacitor should be closest to VCCSYN, followed by the 10-µF capacitor, and finally the 10-

Ω resistor to

Vdd. These traces should be kept short and direct.

PLL

Dividers

PCI Interface

CPM_CLK

BUS_CLK

PCI_CLK

PCI Circuit

60x Circuit

clkin1

dllout

clkin2

60x Bus Clock

PCI Clock

MPC8280

PCI_CLK

DLL

VDD

VCCSYN

0.1uF

10uF

10ohm

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