MPC8280 datasheet(414/1386 Pages) FREESCALE

414 / 1386 page

Clocks and Power Control

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

10-4

Freescale Semiconductor

10.1.6

PCI Bridge as an Agent Operating from the PCI System Clock

If the MPC8280 is connected to a system which generates the PCI clock, the PCI clock should be fed to

the CLKIN1 pin. The PCI clock is internally multiplied by the PLL to generate the chip’s internal high

speed clock. This clock is used to generate the 60x bus clock. The 60x bus clock is then driven by a DLL

circuit to the DLLOUT pin, which has a feedback path from the board to the CLKIN2 pin. This feedback

clock signal is used by the DLL logic to minimize clock skew between the internal and external clocks.

NOTE

All PCI timings are measured relative to CLKIN1; all 60x bus timings are

measured relative to CLKIN2.

Figure 10-2. PCI Bridge as an Agent, Operating from the PCI System Clock

10.1.7

PCI Bridge as a Host Generating the PCI System Clock

In a system where the MPC8280 is the host that generates the PCI clock, the 60x bus clock should be

driven to the CLKIN1 pin. The 60x bus clock is internally multiplied by the PLL to generate the CPM high

speed clock and then internally divided to generate the PCI bus clock. The PCI bus clock is then driven by

the DLL circuit to the DLLOUT pin, which has a feedback path from the board to the CLKIN2 pin. This

feedback controls clock skew by ensuring the same internal and external clock timing.

NOTE

All PCI timings are measured relative to CLKIN2, and all 60x bus timings

are measured relative to CLKIN1.

PLL

Dividers

PCI Interface

CPM_CLK

BUS_CLK

PCI_CLK

60x Circuit

PCI Circuit

clkin1

dllout

clkin2

PCI Clock

Bus Clock

MPC8280

BUS_CLK

DLL

MPC8280 Datasheet(PDF) 414 Page - Freescale Semiconductor, Inc