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MPC8280 Datasheet(PDF) 463 Page - Freescale Semiconductor, Inc |
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MPC8280 Datasheet(HTML) 463 Page - Freescale Semiconductor, Inc |
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463 / 1386 page ![]() Memory Controller MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 11-43 P/LSDMR[BUFCMD] should be set. Setting this bit causes the memory controller to add one cycle for each SDRAM command. Figure 11-27 illustrates the timing when BUFCMD equals 1. Figure 11-27. BUFCMD = 1 11.4.7 SDRAM Interface Timing Figure 11-28 through Figure 11-36 show SDRAM timing for various types of accesses. Figure 11-28. SDRAM Single-Beat Read, Page Closed, CL = 3 CLK SDAMUX CMD strobes MA[0–11] Row Column Activate Read NOP NOP (without cs) CS ALE Command setup cycle Command setup cycle CLK ALE CS SDRAS SDCAS MA[0–11] Row Column WE DQM Data D0 |
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