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MPC8280 Datasheet(PDF) 466 Page - Freescale Semiconductor, Inc |
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MPC8280 Datasheet(HTML) 466 Page - Freescale Semiconductor, Inc |
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466 / 1386 page  Memory Controller MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 11-46 Freescale Semiconductor Figure 11-35. SDRAM Write-after-Write Pipelined, Page Hit Figure 11-36. SDRAM Read-after-Write Pipelined, Page Hit 11.4.8 SDRAM Read/Write Transactions The SDRAM interface supports the following read/write transactions: • Single-beat reads/writes up to double word size • Bursts of two, three, or four double words SDRAM devices perform bursts for each transaction, the burst length depends on the port size. For 64-bit port size, it is a burst of 4. For 32-bit port size, it is a burst of 8. For reads that require less than the full burst length, extraneous data in the burst is ignored. For writes that require less than the full burst length, the MPC8280 protects non-targeted addresses by driving DQMn high on the irrelevant cycles of the burst. However, system performance is not compromised since, if a new transaction is pending, the MPC8280 begins executing it immediately, effectively terminating the burst early. CLK ALE CS SDRAS SDCAS MA[0–11] Column1 WE DQM Data D0 D1 D2 D3 D1 D2 D3 D0 Column2 CLK ALE CS SDRAS SDCAS MA[0–11] Column1 WE DQM Data D0 D1 D2 D3 D1 D2 D3 D0 Column2 Z |
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