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MPC8280 Datasheet(PDF) 459 Page - Freescale Semiconductor, Inc

Part # MPC8280
Description  PowerQUICC??II Family Reference Manual
PDF  1386 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8280 Datasheet(HTML) 459 Page - Freescale Semiconductor, Inc

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Memory Controller
MPC8280 PowerQUICC II Family Reference Manual, Rev. 1
Freescale Semiconductor
11-39
•
Refresh recovery interval (P/LSDMR[RFRC]). See Section 11.4.6.6, “Refresh Recovery Interval
(RFRC).”
•
External address multiplexing present (P/LSDMR[EAMUX]). See Section 11.4.6.7, “External
Address Multiplexing Signal.”
•
External buffers on the control lines present (P/LSDMR[BUFCMD]). See Section 11.4.6.8,
“External Address and Command Buffers (BUFCMD).”
The following sections describe the SDRAM parameters that are programmed in the P/LSDMR register.
11.4.6.1
Precharge-to-Activate Interval
As demonstrated in Figure 11-20, this parameter, controlled by P/LSDMR[PRETOACT] defines the
earliest timing for activate or refresh command after a precharge command.
Figure 11-20. PRETOACT = 2 (2 Clock Cycles)
11.4.6.2
Activate to Read/Write Interval
As represented in Figure 11-21, this parameter, controlled by P/LSDMR[ACTTORW], defines the earliest
timing for READ/WRITE command after an ACTIVATE command.
CLK
ALE
CS
SDRAS
SDCAS
WE
DQM
PRECHARGE
Command
ACTIVATE
MA11
MA10
MA[0–9]
RAy
RAy
Bank A
Command
Bank A
PRETOACT = 2



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