MPC8280 datasheet(457/1386 Pages) FREESCALE

457 / 1386 page

Memory Controller

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

11-37

allowing interleaving on every page boundary. It is activated by setting xSDMR[PBI]=1. See

“0xSDRAM Configuration Example (Page-Based Interleaving)”.

•

Bank-based interleaving —This method uses the most-significant address bits as the bank-select

for the SDRAM, thus allowing interleaving only on bank boundaries. It is activated by clearing

xSDMR[PBI]. See Section 11.4.12, “SDRAM Configuration Examples.”

11.4.5.1

Using BNKSEL Signals in Single-MPC8280 Bus Mode

The BNKSEL signals provide the following functionality in single-MPC8280 bus mode

•

If bank-based interleaving is used, BNKSEL signals facilitate compatibility with SDRAMs that

have different numbers of row or column address lines. The address lines of the MPC8280 bus and

the BNKSEL lines can be routed independently to the address lines and BA lines of the DIMM.

Note that all SDRAMs populated on an MPC8280 bus must still have the same organization. This

flexibility merely allows the SDRAMs to be populated as a group with larger or smaller devices as

appropriate.

If BNKSEL lines were not used, the number of row and column address lines of the SDRAMs

would affect which MPC8280 address bus lines on which the bank select signals would be driven,

and would thus require that the BA signals of the SDRAMs be routed to those address lines, thus

limiting flexibility.

•

If BCR[EAV] is programmed, BNKSEL signals facilitate logic analysis of the system. Otherwise,

the logic analyzer equipment must understand the address multiplexing scheme of the board and

intelligently reconstruct the address of bus transactions.

11.4.5.2

SDRAM Address Multiplexing (SDAM and BSMA)

In single MPC8280 mode, the lower bits of the address bus are connected to the device’s address port, and

the memory controller multiplex the row/column and the internal banks select lines, according to the

PL/SDMR[SDAM] and PL/SDMR[BSMA].

Table 11-20. shows how P/LSDMR[SDAM] settings affect address multiplexing. For the effect of

PL/SDMR[BSMA] see Section 11.4.12, “SDRAM Configuration Examples.”

Note that in 60x-compatible mode, the 60x address must be latched and multiplexed by glue logic that is

controlled by ALE and SDAMUX, however, the user still has to configure PSDMR[SDAM].

On the local bus, only the lower 18 bits of the address are output. Table 11-20 shows SDRAM address

multiplexing for A0–A15.

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