MPC8280 datasheet(455/1386 Pages) FREESCALE

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Memory Controller

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

11-35

11.4.1

Supported SDRAM Configurations

The MPC8280 memory controller supports any SDRAM configuration under the restrictions that all

SDRAM devices that reside on the same bus (60x or local) should have the same port size and timing

parameters. For more information, refer to Application Note 2165, “MPC8260 SDRAM Support” (order

number AN2165/D).

11.4.2

SDRAM Power-On Initialization

At system reset, initialization software must set up the programmable parameters in the memory controller

banks registers (ORx, BRx, P/LSDMR). After all memory parameters are configured, system software

should execute the following initialization sequence for each SDRAM device.

1. Issue a PRECHARGE-ALL-BANKS command

2. Issue eight CBR REFRESH commands. If the SDRAM does not require eight CBR REFRESH

commands, then the SDRAM requirement should be followed.

3. Issue a MODE-SET command to initialize the mode register

The initial commands are executed by setting P/LSDMR[OP] and accessing the SDRAM with a

single-byte transaction. See Figure 11-10 on page 11-20.

Note that software should ensure that no memory operations begin until this process completes.

11.4.3

JEDEC-Standard SDRAM Interface Commands

The MPC8280 performs all accesses to SDRAM by using JEDEC-standard SDRAM interface commands.

The SDRAM device samples the command and data inputs on the rising edge of the MPC8280 bus clock.

Data at the output of the SDRAM device must be sampled on the rising edge of the MPC8280 bus clock.

As seen in Table 11-19, the MPC8280 provides the following SDRAM interface commands:

Table 11-19. SDRAM Interface Commands

Command

Description

Bank-activate

Latches the row address and initiates a memory read of that row. Row data is latched in SDRAM

sense amplifiers and must be restored with a PRECHARGE command before another BANK-ACTIVATE

is issued.

Mode-set

Allows setting of SDRAM options—CAS latency, burst type, and burst length. CAS latency depends

on the SDRAM device used (some SDRAMs provide CAS latency of 1, 2, or 3; some provide a

latency of 1, 2, 3, or 4, etc.). Burst type must be chosen according to the 60x cache wrap

(sequential). Although some SDRAMs provide burst lengths of 1, 2, 4, 8, or a page, MPC8280

supports only a 4-beat burst for 64-bit port size and an 8-beat burst for 32-bit port size. MPC8280

does not support burst lengths of 1, 2, and a page for SDRAMs. The mode register data (CAS

latency, burst length, and burst type) is programmed into the P/LSDMR register by initialization

software at reset. After the P/LSDMR is set, the MPC8280 transfers the information to the SDRAM

array by issuing a MODE-SET command. Section 11.4.9, “SDRAM Mode-Set Command Timing,”

gives timing information.

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