MPC8280 datasheet(456/1386 Pages) FREESCALE

456 / 1386 page

Memory Controller

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

11-36

Freescale Semiconductor

11.4.4

Page-Mode Support and Pipeline Accesses

The SDRAM interface supports back-to-back page mode. A page remains open as long as back-to-back

accesses that hit the page are generated on the bus. The page is closed once the bus becomes idle unless

ORx[PMSEL] is set.

The use of SDRAM pipelining allows data phases to occur on with zero bubbles for CPM accesses and

with one bubble for core accesses, as required by the 60x bus specification.

If ETM/LETM = 1, the use of SDRAM pipelining also allows for back-to-back data phases to occur with

zero clocks of separation for CPM accesses and with one clock of separation for core accesses, as required

by the 60x bus specification.

11.4.5

Bank Interleaving

The SDRAM interface supports bank interleaving. This means that if a missed page is in a different

SDRAM bank than the currently open page, the SDRAM machine first issues an ACTIVATE command to

the new page and later issues a DEACTIVATE command to the old page, thus eliminating the DEACTIVATE

time overhead.

This procedure can be done if both pages reside on different SDRAM devices or on different internal

SDRAM banks. The second option can be disabled by setting ORx[IBID]. The user should set this bit if

the BNKSEL pins are not used in 60x-compatible mode.

The following two methods are used for internal bank interleaving:

•

Page-based interleaving—Page-based interleaving yields the best performance and is the preferred

interleaving method. This method uses low address bits as the Bank-Select for the SDRAM, thus

Precharge

(single bank/all

banks)

Restores data from the sense amplifiers to the appropriate row. Also initializes the sense amplifiers

to prepare for reading another row in the SDRAM array. A PRECHARGE command must be issued

after a read or write if the row address changes on the next access. Note that the MPC8280 uses

the SDA10 pin to distinguish the PRECHARGE-ALL-BANKS command. The SDRAMs must be

compatible with this format.

Read

Latches the column address and transfers data from the selected sense amplifier to the output buffer

as determined by the column address. During each successive clock, additional data is output

without additional READ commands. The amount of data transferred is determined by the burst size.

At the end of the burst, the page remains open.

Refresh

Causes a row to be read in both memory banks (JEDEC SDRAM) as determined by the refresh row

address counter (similar to CBR). The refresh row address counter is internal to the SDRAM device.

After being read, a row is automatically rewritten into the memory array. Both banks must be in a

precharged state before executing REFRESH.

Write

Latches the column address and transfers data from the data signals to the selected sense amplifier

as determined by the column address. During each successive clock, additional data is transferred

to the sense amplifiers from the data signals without additional WRITE commands. The amount of

data transferred is determined by the burst size. At the end of the burst, the page remains open.

Table 11-19. SDRAM Interface Commands (continued)

Command

Description

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