MPC8280 datasheet(479/1386 Pages) FREESCALE

479 / 1386 page

Memory Controller

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

11-59

11.5.1.5

Programmable Wait State Configuration

The GPCM supports internal PSDVAL generation. It allows fast accesses to external memory through an

internal bus master or a maximum 17-clock access by programming ORx[SCY]. The internal PSDVAL

generation mode is enabled if ORx[SETA] = 0. If GTA is asserted externally at least two clock cycles

before the wait state counter has expired, the current memory cycle is terminated. When TRLX = 1, the

number of wait states inserted by the memory controller is defined by 2 x SCY or a maximum of 30 wait

states.

11.5.1.6

Extended Hold Time on Read Accesses

Slow memory devices that take a long time to turn off their data bus drivers on read accesses should choose

some combination of ORx[29–30] (TRLX and EHTR). Any access following a read access to the slower

memory bank is delayed by the number of clock cycles specified by Table 11-32.

See Figure 11-50 through Figure 11-53 for timing examples.

Figure 11-50. GPCM Read Followed by Read (OR

x[29–30] = 00, Fastest Timing)

Table 11-32. TRLX and EHTR Combinations

ORx[TRLX] ORx[EHTR]

Number of Hold Time

Clock Cycles

Clock

Address

PSDVAL

CSx

CSy

BCTL

Data

MPC8280 Datasheet(PDF) 479 Page - Freescale Semiconductor, Inc