MPC8280 datasheet(483/1386 Pages) FREESCALE

483 / 1386 page

Memory Controller

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

11-63

11.5.4

Differences Between the MPC8

xx GPCM and MPC82xx GPCM

Users familiar with the MPC8xx GPCM should read this section first:

•

External termination—In the MPC8xx the external termination connects to the external bus TA and

so must be asserted in sync with the system clock. In the MPC8280, this signal is separated from

the bus and named GTA. The signal is synchronized internally and sampled. The sampled signal is

used to generate TA, which terminates the bus transaction.

•

Extended hold time for reads can be up to 8 clock cycles (instead of 1 in the MPC8xx).

11.6

User-Programmable Machines (UPMs)

Users familiar with MPC8xx memory controller should first read Section 11.6.6, “Differences Between

the MPC8xx UPM and MPC82xx UPM.” Table 11-34 lists the UPM interface signals on the 60x and local

bus.

OR0

1111_1110_0000_0000_0 (32 MByte)

BCTLD

CSNT

ACS

SCY

1111

SETA

TRLX

EHTR

Table 11-34. UPM Interfaces Signals

60x Bus

Local Bus

Comments

CS[0–11]

Device select

PBS[0–7]

LBS[0–3]

Byte Select

PGPL_0

LGPL_0

General-purpose line

PGPL_1

LGPL_1

General-purpose line

PGPL_2

LGPL_2

General-purpose line

PGPL_3

LGPL_3

General-purpose line

PGPL_4/UPMWAIT

LGPL_4/UPMWAIT

General-purpose line

4/UPM wait

PGPL_5

LGPL_5

General-purpose line

Table 11-33. Boot Bank Field Values after Reset (continued)

Setting

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