MPC8280 datasheet(487/1386 Pages) FREESCALE

487 / 1386 page

Memory Controller

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

11-67

only one refresh routine should be programmed for the 60x bus and be placed in UPMA, which serves as

the 60x bus refresh executor. If refresh is not required on the 60x bus, UPMA can be assigned to any bus.

All local bus refreshes are done using the refresh pattern of UPMB. This means that if refresh is required

on the local bus, UPMB must be assigned to the local bus and MBMR[RFEN] must be set. It also means

that only one refresh routine should be programmed for the local bus, and be placed in UPMB, which

serves as the local bus refresh executor. If refresh is not required on the local bus, UPMB can be assigned

to any bus.

UPMC can be assigned to any bus; there is no need to program its refresh routine because it will use the

one in UPMA or UPMB, according to the bus to which it is assigned.

11.6.1.3

Software Requests—RUN Command

Software can start a request to the UPM by issuing a RUN command to the UPM. Some memory devices

have their own signal handshaking protocol to put them into special modes, such as self-refresh mode.

Other memory devices require special commands to be issued on their control signals, such as for SDRAM

initialization.

For these special cycles, the user creates a special RAM pattern that can be stored in any unused areas in

the UPM RAM. Then the RUN command is used to run the cycle. The UPM runs the pattern beginning at

the specified RAM location until it encounters a RAM word with its LAST bit set. The RUN command is

issued by setting MxMR[OP] = 11 and accessing the UPMx memory region with a single-byte transaction.

Note that the pattern must contain exactly one assertion of PSDVAL (UTA bit in the RAM word, described

in Table 11-36.), otherwise bus time-out may occur.

11.6.1.4

Exception Requests

When the MPC8280 under UPM control initiates an access to a memory device, the external device may

assert TEA or SRESET. The UPM provides a mechanism by which memory control signals can meet the

timing requirements of the device without losing data. The mechanism is the exception pattern that defines

how the UPM deasserts its signals in a controlled manner.

11.6.2

Programming the UPMs

The UPM is a microsequencer that requires microinstructions or RAM words to generate signal timings

for different memory cycles. Follow these steps to program the UPMs:

1. Set up BRx and ORx.

2. Write patterns into the RAM array.

3. Program MPTPR and L/PURT if refresh is required.

4. Program the machine mode register (MxMR).

Patterns are written to the RAM array by setting MxMR[OP] = 01 and accessing the UPM with a single

byte transaction. See Figure 11-11.

MPC8280 Datasheet(PDF) 487 Page - Freescale Semiconductor, Inc