MPC8280 datasheet(485/1386 Pages) FREESCALE

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Memory Controller

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

11-65

11.6.1

Requests

An internal or external device’s request for a memory access initiates one of the following patterns

(MxMR[OP] = 00):

•

Read single-beat pattern (RSS)

•

Read burst cycle pattern (RBS)

•

Write single-beat pattern (WSS)

•

Write burst cycle pattern (WBS)

These patterns are described in Section 11.6.1.1, “Memory Access Requests.”

A UPM refresh timer request pattern initiates a refresh timer pattern (PTS), as described in

Section 11.6.1.2, “UPM Refresh Timer Requests.”

An exception (caused by a soft reset or the assertion of TEA) occurring while another UPM pattern is

running initiates an exception condition pattern (EXS).

A special pattern in the RAM array is associated with each of these cycle type. Figure 11-56 shows the

start addresses of these patterns in the UPM RAM, according to cycle type. RUN commands (MxMR[OP]

= 11), however, can initiate patterns starting at any of the 64 UPM RAM words.

Figure 11-56. RAM Array Indexing

Write Single-Beat Request

Read Burst Request

Read Single-Beat Request

Write Burst Request

RAM Array

Refresh Timer Request

Exception Condition Request

RSS

RBS

WSS

WBS

PTS

EXS

64 RAM

Words

Array Index

Generator

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