MPC8280 datasheet(486/1386 Pages) FREESCALE

486 / 1386 page

Memory Controller

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

11-66

Freescale Semiconductor

Table 11-35 show the start address of each pattern.

11.6.1.1

Memory Access Requests

When an internal device requests a new access to external memory, the address of transfer is compared to

each valid bank defined in BRx. The value in BRx[MS] selects the UPM to handle the memory access. The

user must ensure that the UPM is appropriately initialized before a request.

The UPM supports two types of memory reads and writes:

•

A single-beat transfer transfers one operand consisting of up to double word. A single-beat cycle

starts with one transfer start and ends with one transfer acknowledge.

•

A burst transfer transfers four double words. For 64-bit accesses, the burst cycle starts with one

transfer start but ends after four transfer acknowledges. A 32-bit device requires 8 data

acknowledges; an 8-bit device requires 32. See Section 11.2.13, “Partial Data Valid Indication

(PSDVAL).”

The MPC8280 defines two additional transfer sizes: bursts of two and three double words. These accesses

are treated by the UPM as back-to-back, single-beat transfers.

11.6.1.2

UPM Refresh Timer Requests

Each UPM contains a refresh timer that can be programmed to generate refresh service requests of a

particular pattern in the RAM array. Figure 11-57 shows the hardware associated with memory refresh

timer request generation. PURT defines the period for the timers associated with UPMx on the 60x bus and

LURT defines it on the local bus. See Section 11.3.8, “60x Bus-Assigned UPM Refresh Timer (PURT),”

and Section 11.3.9, “Local Bus-Assigned UPM Refresh Timer (LURT).”

Figure 11-57. Memory Refresh Timer Request Block Diagram

All 60x bus refreshes are done using the refresh pattern of UPMA. This means that if refresh is required

on the 60x bus, UPMA must be assigned to the 60x bus and MAMR[RFEN] must be set. It also means that

Table 11-35. UPM Routines Start Addresses

UPM Routine

Routine Start Address

Read single-beat (RSS)

0x00

Read burst (RBS)

0x08

Write single-beat (WSS)

0x18

Write burst (WBS)

0x20

Refresh timer (PTS)

0x30

Exception condition (EXS)

0x3C

60x bus assigned UPM

Local bus assigned UPM

Bus

Divide by PURT

PTP Prescaling

Divide by LURT

refresh timer request

Clock

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