MPC8280 datasheet(489/1386 Pages) FREESCALE

489 / 1386 page

Memory Controller

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

11-69

Figure 11-59. Memory Controller UPM Clock Scheme for Non-Integer (2.5:1/3.5:1)

Clock Ratios

The state of the external signals may change (if specified in the RAM array) at any positive edge of T1,

T2, T3, or T4 (there is a propagation delay specified in the Hardware Specifications). Note however that

only the CS signal corresponding to the currently accessed bank is manipulated by the UPM pattern when

it runs. The BS signal assertion and negation timing is also specified for each cycle in the RAM word;

which of the four BS signals are manipulated depends on the port size of the specified bank, the external

address accessed, and the value of TSIZn. The GPL lines toggle as programmed for any access that

initiates a particular pattern, but resolution of control is limited to T1 and T3.

Figure 11-60 shows how CSx, GPL1, and GPL2 can be controlled. A word is read from the RAM that

specifies on every clock cycle the logical bits CST1, CST2, CST3, CST4, G1T1, G1T3, G2T1, and G2T3.

These bits indicate the electrical value for the corresponding output pins at the appropriate timing.

CLKIN

MPC8280 Datasheet(PDF) 489 Page - Freescale Semiconductor, Inc