MPC8280 datasheet(494/1386 Pages) FREESCALE

494 / 1386 page

Memory Controller

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

11-74

Freescale Semiconductor

G5T1

General-purpose line 5 timing 1. Defines the state of GPL5 during phase 1–2.

0 The value of the GPL5 line at the rising edge of T1 will be 0

1 The value of the GPL5 line at the rising edge of T1 will be 1

G5T3

General-purpose line 5 timing 3. Defines the state of GPL5 during phase 3–4.

0 The value of the GPL5 line at the rising edge of T3 will be 0

1 The value of the GPL5 line at the rising edge of T3 will be 1

22–23

REDO Redo current RAM word. See “Section 11.6.4.1.5, “Repeat Execution of Current RAM Word

(REDO).”

00 Normal operation

01 The current RAM word is executed twice.

10 The current RAM word is executed tree times.

11 The current RAM word is executed four times.

Note: For Rev A.1 and forward: for any value other than 00, do not use REDO on two consecutive

CPM RAM words. The second word will not execute.

LOOP

Loop. The first RAM word in the RAM array where LOOP is 1 is recognized as the loop start word.

The next RAM word where LOOP is 1 is the loop end word. RAM words between the start and end

are defined as the loop. The number of times the UPM executes this loop is defined in the

corresponding loop field of the M

xMR.

0 The current RAM word is not the loop start word or loop end word.

1 The current RAM word is the start or end of a loop.

See Section 11.6.4.1.4, “Loop Control.”

EXEN

Exception enable. If an external device asserts TEA or RESET, EXEN allows branching to an

exception pattern at the exception start address (EXS) at a fixed address in the RAM array.

When the MPC8280 under UPM control begins accessing a memory device, the external device

may assert TEA or SRESET. An exception occurs when one of these signals is asserted by an

external device and the MPC8280 begins closing the memory cycle transfer. When one of these

exceptions is recognized and EXEN in the RAM word is set, the UPM branches to the special

exception start address (EXS) and begins operating as the pattern defined there specifies. See

Table 11-35.. The user should provide an exception pattern to deassert signals controlled by the

UPM in a controlled fashion. For DRAM control, a handler should negate RAS and CAS to prevent

data corruption. If EXEN = 0, exceptions are deferred and execution continues. After the UPM

branches to the exception start address, it continues reading until the LAST bit is set in the RAM

word.

0 The UPM continues executing the remaining RAM words.

1 The current RAM word allows a branch to the exception pattern after the current cycle if an

exception condition is detected. The exception condition can be an external device asserting TEA

or SRESET.

26–27

AMX

Address multiplexing. Determines the source of A[0–31] at the rising edge of t1 (single-MPC8280

mode only). See Section 11.6.4.2, “Address Multiplexing.”

00 A[0–31] is the non-multiplexed address. For example, column address.

01 Reserved.

10 A[0–31] is the address requested by the internal master multiplexed according to M

xMR[AMx].

For example, row address.

11 A[0–31] is the contents of MAR. Used for example, during SDRAM mode initialization.

Table 11-36. RAM Word Bit Settings (continued)

Bit

Name

Description

MPC8280 Datasheet(PDF) 494 Page - Freescale Semiconductor, Inc

MPC8280 Datasheet(HTML) 494 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL