MPC8280 datasheet(498/1386 Pages) FREESCALE

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Memory Controller

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

11-78

Freescale Semiconductor

11.6.4.2

Address Multiplexing

The address lines can be controlled by the pattern the user provides in the UPM. The address multiplex

bits can choose between outputting an address requested by the internal master as is and outputting it

according to the multiplexing specified by the MxMR[AMx]. The last option is to output the contents of

the MAR on the address pins.

Note that in 60x-compatible mode, MAR cannot be output on the 60x bus external address line.

Note that on the local bus, only the lower 18 bits of the MAR are output.

Also, note that for the UPM address multiplexing to work, if the UPM is on the 60x bus, PSDMR[PBI]

needs to be zero. If the UPM is on the local bus, LSDMR[PBI] needs to be zero. This means that UPM

address multiplexing does not work when the SDRAM controller is on the same bus and PBI is set to one.

Table 11-38 shows how MxMR[AMx] settings affect address multiplexing.

See Section 11.6.5, “UPM DRAM Configuration Example,” for more details.

11.6.4.3

Data Valid and Data Sample Control

When a read access is handled by the UPM and the UTA bit is 1, the value of the DLT3 bit in the same

RAM word indicates when the data input is sampled by the internal bus master, assuming that

MxMR[GPLx4DIS] = 1.

•

If G4T4/DLT3 functions as DLT3 and DLT3 = 1 in the RAM word, data is latched on the falling

edge of CLKIN instead of the rising edge. The data is sampled by the internal master on the next

rising edge as is required by the MPC8280 bus operation spec. This feature lets the user speed up

the memory interface by latching data 1/2 clock early, which can be useful during burst reads. This

feature should be used only in systems without external synchronous bus devices.

•

If G4T4/DLT3 functions as G4T4, data is latched on the rising edge of CLKIN, as is normal in

MPC8280 bus operation.

Figure 11-65 shows data sampling that is controlled by the UPM.

Table 11-38. UPM Address Multiplexing

External Bus

Address Pin

A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31

000

Signal Driven

on External

Pin when

Address

Multiplexing

is Enabled

A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23

001

A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22

010

A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21

011

A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20

100

—

A10 A11 A12 A13 A14 A15 A16 A17 A18 A19

101

—

A10 A11 A12 A13 A14 A15 A16 A17 A18

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