MPC8280 datasheet(500/1386 Pages) FREESCALE

Part #	MPC8280

Description	PowerQUICC??II Family Reference Manual

PDF	1386 Pages

Scroll/Zoom	100%

Manufacturer	FREESCALE [Freescale Semiconductor, Inc]

Direct Link	http://www.freescale.com

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500 / 1386 page

Memory Controller

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

11-80

Freescale Semiconductor

Figure 11-66. Wait Mechanism Timing for Internal and External Synchronous Masters

11.6.4.6

Extended Hold Time on Read Accesses

Slow memory devices that take a long time to turn off their data bus drivers on read accesses should chose

some combination of ORx[EHTR]. Accesses after a read access to the slower memory bank is delayed by

the number of clock cycles specified by Table 11-32. The information in Section 11.5.1.6, “Extended Hold

Time on Read Accesses,” provides additional information.

11.6.5

UPM DRAM Configuration Example

Consider the following DRAM organization:

•

Eight 64Mbit devices, each organized as 8M x 8bits

•

Each device has 12 row lines and 9 column lines.

CSx

GPL1

WAEN

Word n

Word n+1

UPMWAIT

c9 c10 c11

c12

c13 c14

Word n+2

Wait

Word n+3

PSDVAL

CLKIN

MPC8280 Datasheet(PDF) 500 Page - Freescale Semiconductor, Inc