MPC8280 datasheet(593/1386 Pages) FREESCALE

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Serial Interface with Time-Slot Assigner

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

15-15

15.4.5

Static and Dynamic Routing

The SIx RAM has two operating modes for the TDMs:

•

Static routing. The number of SIx RAM entries is determined by the banks the user relates to the

corresponding TDM and is divided into two parts (Rx and Tx). The following sequence must be

followed to program the routing entries.

— All serial devices connected to the TSA must be disabled.

— SI routing can be modified.

— All appropriate serial devices connected to the TSA must be reenabled.

•

Dynamic routing. A TDM’s routing definition can be modified while FCCs, MCCs, SCCs, or

SMCs are connected to the TDM. The number of SIx RAM entries is determined by the banks the

user relates to the corresponding TDM channel and is divided into four parts (Rx, Rx shadow, Tx,

and Tx shadow).

Dynamic changes divide portions of the SIx RAM into current-route and shadow RAM. Once the

current-route RAM is programmed, the TSA and SI channels are enabled, and TSA operation begins.

When a change in routing is required, the shadow RAM must be programmed with the new route and

SIxCMDR[CSRxn] must be set. As a result, as soon as the corresponding sync arrives the SI exchanges

the shadow RAM with the current-route RAM and resets CSRxn to indicate that the operation is complete.

At this time, the user may change the routing again. Notice that the original current-route RAM is now the

shadow RAM and vice versa. Figure 15-9. shows an example of the shadow RAM exchange process for

two TDM channels both with half of the RAM as a shadow.

If for instance one TDM with dynamic changes is programmed to own all four banks, and the shadow is

programmed to the last two banks, the initial current-route RAM addresses in the SIx RAM are as follows.

•

0–255: TXa route

•

1024–1279: RXa route

The initial shadow RAMs are at addresses:

•

256–511: TXa route

•

1280–1535: RXa route

The user can read any RAM at any time, but for proper SI operation the user must not attempt to write the

current-route RAM. The SIx status register (SIxSTR) can be read to find out which part of the RAM is the

current-route RAM. The user can also externally connect one of the strobes to an interrupt pin to generate

an interrupt on a particular SIx RAM entry starting or ending execution by the TSA.

NOTE

The current-route and shadow SI RAMs of a given TDMx should be

contiguous; that is, the current-route and shadow SI RAMs of differing

TDMx should not be interleaved. An example is shown in Figure 15-9.

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